Patents by Inventor Ravi Dixit
Ravi Dixit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220188475Abstract: The present document describes techniques associated with a textile-material model for vibroacoustic structural simulation. The techniques described herein provide a nontrivial methodology to test a textile and simplify its representation, which can enable prediction of acoustic performance (e.g., rub and buzz) of an electronic-speaker device having a textile mounted thereon. The textile is modeled as a textile-material model based on an elongation stiffness obtained from a time-temperature superposition curve of the textile, which is based on a dynamic mechanical analysis test of the textile in each of course and wale directions. The textile-material model is then applied to an assembly model of the electronic-speaker device to simulate a vibroacoustic response of the textile relative to the assembly model to predict a likelihood of rub and buzz.Type: ApplicationFiled: December 15, 2020Publication date: June 16, 2022Applicant: Google LLCInventors: Laura Charlotte Shumaker, Arun Prakash Raghupathy, Ayyana Mori Chakravartula, Darren Torrie, Janet P. Ho, Liang Cheng, Neha Ravi Dixit, Paul L. Briant, Kaitlin S. Spak, Gunjan Agarwal, Daniel Mennitt
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Publication number: 20220102691Abstract: A battery pack includes a battery, an outer enclosure housing the battery to form a battery pack, and an expandable portion extending from the outer enclosure and allowing the battery pack to expand along an X-axis of the battery pack. The expandable portion includes an inner portion, an outer portion, and a gap portion between the inner portion and the outer portion. The inner portion and the outer portion have a sealing layer to seal off an interior space and the gap portion is devoid of the sealing layer. The sealing layer allows for fluid communication between the gap portion and the interior space when a pressure exerted on the sealing layer exceeds a pressure threshold. The expandable portion includes folds allowing the expandable portion to fold toward the battery pack in an initial folded configuration and expand away from the battery pack in an at least partially unfolded configuration.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Applicant: Google LLCInventors: David Wang, Lauren Francine Chanen, James Robert Lim, Neha Ravi Dixit, Alexander P. Wroblewski
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Publication number: 20210410334Abstract: The present document describes a passive thermal-control structure for speakers and associated apparatuses and methods. The architecture of the passive thermal-control structure is such that heat is transferred from electronic subsystems of the electronic speaker device to the passive thermal-control structure, which acts as an internal, structural frame of the electronic speaker device and provides both thermal mitigation and structural stability. The passive thermal-control structure conducts heat from the electronic subsystems to a housing of the electronic speaker device.Type: ApplicationFiled: August 20, 2021Publication date: December 30, 2021Applicant: Google LLCInventors: Emil Rahim, Ihab A. Ali, Phanindraja Ancha, Neha Ravi Dixit
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Publication number: 20210410332Abstract: The present document describes a passive thermal-control structure for speakers and associated apparatuses and methods. The architecture of the passive thermal-control structure is such that heat is transferred from electronic subsystems of the electronic speaker device to the passive thermal-control structure, which acts as an internal, structural frame of the electronic speaker device and provides both thermal mitigation and structural stability. The passive thermal-control structure conducts heat from the electronic subsystems to a housing of the electronic speaker device. The housing of the electronic speaker device may dissipate the heat to the ambient environment to prevent thermal runaway of the electronic subsystems, and the internal frame mitigates the temperature of the housing from exceeding ergonomic temperature limits.Type: ApplicationFiled: June 29, 2020Publication date: December 30, 2021Applicant: Google LLCInventors: Emil Rahim, Ihab A. Ali, Phanindraja Ancha, Neha Ravi Dixit
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Patent number: 11212940Abstract: The present document describes a passive thermal-control structure for speakers and associated apparatuses and methods. The architecture of the passive thermal-control structure is such that heat is transferred from electronic subsystems of the electronic speaker device to the passive thermal-control structure, which acts as an internal, structural frame of the electronic speaker device and provides both thermal mitigation and structural stability. The passive thermal-control structure conducts heat from the electronic subsystems to a housing of the electronic speaker device. The housing of the electronic speaker device may dissipate the heat to the ambient environment to prevent thermal runaway of the electronic subsystems, and the internal frame mitigates the temperature of the housing from exceeding ergonomic temperature limits.Type: GrantFiled: June 29, 2020Date of Patent: December 28, 2021Assignee: Google LLCInventors: Emil Rahim, Ihab A. Ali, Phanindraja Ancha, Neha Ravi Dixit
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Patent number: 11099593Abstract: An integrated circuit includes a base current cancellation circuit and a complementary to absolute temperature (CTAT) circuit. The base current cancellation circuit includes a first bipolar junction transistor (BJT) and a current mirror coupled to the first BJT. The current mirror is configured to provide a mirrored current to a base electrode of the first BJT. The CTAT circuit is coupled to receive a voltage signal corresponding to a reference current of the current mirror. The CTAT circuit includes a second BJT coupled to form a base current based on the voltage signal.Type: GrantFiled: November 14, 2017Date of Patent: August 24, 2021Assignee: NXP USA, INC.Inventors: Anil Kumar Gottapu, Sanjay Kumar Wadhwa, Ravi Dixit
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Patent number: 10496122Abstract: An integrated circuit includes an output driver circuit configured to provide a first voltage at an output terminal. The output driver circuit includes a transistor having a first current electrode coupled at a voltage supply terminal and a second current electrode coupled at the output terminal, and a resistor having a first terminal coupled at the output terminal and a second terminal coupled at a first node. An amplifier circuit is coupled to the output driver circuit and is configured to generate a proportional to absolute temperature (PTAT) current in a first circuit branch of the output driver circuit coupled at the first node. A complementary to absolute temperature (CTAT) circuit is configured to generate a CTAT current in a second circuit branch coupled at the first node.Type: GrantFiled: August 22, 2018Date of Patent: December 3, 2019Assignee: NXP USA, INC.Inventors: Anil Kumar Gottapu, Sanjay Kumar Wadhwa, Ravi Dixit
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Publication number: 20190146542Abstract: An integrated circuit includes a base current cancellation circuit and a complementary to absolute temperature (CTAT) circuit. The base current cancellation circuit includes a first bipolar junction transistor (BJT) and a current mirror coupled to the first BJT. The current mirror is configured to provide a mirrored current to a base electrode of the first BJT. The CTAT circuit is coupled to receive a voltage signal corresponding to a reference current of the current mirror. The CTAT circuit includes a second BJT coupled to form a base current based on the voltage signal.Type: ApplicationFiled: November 14, 2017Publication date: May 16, 2019Inventors: ANIL KUMAR GOTTAPU, SANJAY KUMAR WADHWA, RAVI DIXIT
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Publication number: 20170023958Abstract: A voltage regulator includes an error amplifier, a voltage buffer, a transistor, a frequency compensation circuit, a capacitor, and a resistive network. The error amplifier receives a reference signal and a feedback signal, and generates an intermediate control signal. The voltage buffer receives the intermediate control signal and generates a control signal. The transistor has a gate that receives the control signal, a first terminal that receives a supply voltage signal, and a second terminal that generates a regulated output signal. The frequency compensation circuit is connected to the second terminal of the transistor. The capacitor is connected to the error amplifier and the frequency compensation circuit. The resistive network receives the regulated output signal and generates the feedback signal.Type: ApplicationFiled: July 26, 2015Publication date: January 26, 2017Inventors: RAVI DIXIT, PARUL K. SHARMA
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Patent number: 9552004Abstract: A voltage regulator includes an error amplifier, a voltage buffer, a transistor, a frequency compensation circuit, a capacitor, and a resistive network. The error amplifier receives a reference signal and a feedback signal, and generates an intermediate control signal. The voltage buffer receives the intermediate control signal and generates a control signal. The transistor has a gate that receives the control signal, a first terminal that receives a supply voltage signal, and a second terminal that generates a regulated output signal. The frequency compensation circuit is connected to the second terminal of the transistor. The capacitor is connected to the error amplifier and the frequency compensation circuit. The resistive network receives the regulated output signal and generates the feedback signal.Type: GrantFiled: July 26, 2015Date of Patent: January 24, 2017Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Ravi Dixit, Parul K. Sharma
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Patent number: 9483435Abstract: A Universal Serial Bus (USB) controller includes a USB transceiver to detect a high-speed (HS) disconnect between the USB controller and a device connected to it. The USB transceiver includes a reference-voltage generation circuit, a HS current driver, first and second comparators, and a multiplexer. The reference-voltage generation circuit generates HS disconnect and transmitter reference-voltage signals that have a constant voltage difference. The first comparator receives DP and DM signals that correspond to a HS Start of Frame (SOF) packet during HS disconnect detection, and generates a control voltage. The multiplexer outputs at least one of the DP and DM signals based on the logic state of the control voltage. The second comparator receives the selected signal and the HS disconnect reference-voltage signal, and outputs a HS disconnect output voltage signal when the selected signal is greater than the HS disconnect reference-voltage signal.Type: GrantFiled: July 6, 2014Date of Patent: November 1, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Ravi Dixit, Parul K. Sharma
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Publication number: 20160004661Abstract: A Universal Serial Bus (USB) controller includes a USB transceiver to detect a high-speed (HS) disconnect between the USB controller and a device connected to it. The USB transceiver includes a reference-voltage generation circuit, a HS current driver, first and second comparators, and a multiplexer. The reference-voltage generation circuit generates HS disconnect and transmitter reference-voltage signals that have a constant voltage difference. The first comparator receives DP and DM signals that correspond to a HS Start of Frame (SOF) packet during HS disconnect detection, and generates a control voltage. The multiplexer outputs at least one of the DP and DM signals based on the logic state of the control voltage. The second comparator receives the selected signal and the HS disconnect reference-voltage signal, and outputs a HS disconnect output voltage signal when the selected signal is greater than the HS disconnect reference-voltage signal.Type: ApplicationFiled: July 6, 2014Publication date: January 7, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Ravi Dixit, Parul K. Sharma
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Patent number: 9065441Abstract: A circuit for scaling down first and second input voltages includes first and second voltage scale-down circuits that scale down the first and second input voltages, respectively. The first voltage scale-down circuit includes a transistor that receives the first input voltage at its gate and, operating in a source-follower configuration, scales down the first input voltage to generate a first output voltage at its source. The second voltage scale-down circuit is identical to the first voltage scale-down circuit and generates a second output voltage based on the second input voltage.Type: GrantFiled: February 5, 2013Date of Patent: June 23, 2015Assignee: FREESCALE SEMICONDUCOTR, INC.Inventors: Nidhi Chaudhry, Ravi Dixit, Parul K. Sharma
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Publication number: 20140217825Abstract: A circuit for scaling down first and second input voltages includes first and second voltage scale-down circuits that scale down the first and second input voltages, respectively. The first voltage scale-down circuit includes a transistor that receives the first input voltage at its gate and, operating in a source-follower configuration, scales down the first input voltage to generate a first output voltage at its source. The second voltage scale-down circuit is identical to the first voltage scale-down circuit and generates a second output voltage based on the second input voltage.Type: ApplicationFiled: February 5, 2013Publication date: August 7, 2014Inventors: Nidhi Chaudhry, Ravi Dixit, Parul K. Sharma
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Publication number: 20070021567Abstract: The invention relates to a polyethylene composition with a bimodal molecular weight distribution, methods for making the same, and articles made therefrom, such as high topload blow moldings and transmission and distribution pipes. The composition comprises a low-molecular-weight (LMW) ethylene homopolymer component and a homogeneous, high-molecular-weight (HMW) ethylene interpolymer component, wherein the LMW component is characterized as having a molecular weight distribution, MWDL, of less than about 8. In some embodiments, the HMW component is characterized by a reverse comonomer distribution.Type: ApplicationFiled: June 30, 2006Publication date: January 25, 2007Applicant: Dow Global Technologies Inc.Inventors: Jozef Van Dun, Peter van den Berghe, Patrick Schouterden, Ruddy Nicasy, Johan Vanvoorden, Frederik Gemoets, Kalyan Sehanobish, Noorallah Jivraj, Ravi Dixit