Patents by Inventor Ravi Kiran Kandikonda
Ravi Kiran Kandikonda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240168678Abstract: Methods, systems, and devices for techniques for performing write operations are described. A controller of a memory system may generate a first command to write first data to a first set of memory cells of a memory array of the memory system. The controller may transmit the first command to a first buffer of the memory system. The first buffer may receive the first command and may generate the first data based on second data from a first address of a register. The first buffer may transmit the first data to the first set of memory cells, via a first buffer, based on the first command.Type: ApplicationFiled: September 29, 2023Publication date: May 23, 2024Inventors: Ravi Kiran Kandikonda, Kallol Mazumder
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Patent number: 11209994Abstract: A memory device includes a data path having a data bus. The memory device further includes a first one-hot communications interface communicatively coupled to the data bus, and a second one-hot communications interface communicatively coupled to the data bus. The memory device additionally includes at least one memory bank, and an input/output (I/O) interface communicatively coupled to the at least one memory bank via the first one-hot communications interface and the second one-hot communications interface, wherein the first one-hot communications interface is configured to convert a first data pattern received by the I/O interface into one-hot signals transmitted via the data bus to the second one-hot communications interface, and wherein the second one-hot communications interface is configured to convert the one-hot signals into the first data pattern to be stored in the at least one memory bank.Type: GrantFiled: December 30, 2019Date of Patent: December 28, 2021Assignee: Micron Technology, Inc.Inventor: Ravi Kiran Kandikonda
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Patent number: 10872658Abstract: Aspects of the present disclosure eliminating the need for a memory device to have both a shifter that shifts input pin values from an input domain into a parity domain and another shifter that shifts a decoded command from the input domain into the parity domain. A memory device can achieve this by, when parity is being performed, shifting the input from the input pins into the parity domain prior to decoding the command. Using a multiplexer, the decoder can receive the command pin portion of the shifted input when parity checking is being performed and can receive the un-shifted command pin input when parity checking is not being performed. The decoder can use the command pin portion of the shifted input to generate shifted and decoded commands or can use the un-shifted command pin input to generate decoded commands.Type: GrantFiled: May 18, 2019Date of Patent: December 22, 2020Assignee: Micron Technology, Inc.Inventors: Jason M. Brown, Vijayakrishna J. Vankayala, William C. Waldrop, Kallol Mazumder, Byung S. Moon, Ravi Kiran Kandikonda
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Patent number: 10747470Abstract: A dynamic random-access memory (DRAM) device includes memory banks configured to store data and provide access to the stored data; and a data control circuit coupled to the memory banks, the data control circuit configured to: determine a pointer based on a received command, wherein the pointer corresponds to a target memory bank associated with the received command, and route a set of bits to or from the target memory bank using the pointer. In the long burst length and page mode operations where the array access is targeted in certain Bank Group, the pointer is generated and then allow the groups of data bits flowing through the center freely. This pseudo flow through scheme is low power and fast speed by removing the control of gating commands at each stage of the data path during Read and Write operations.Type: GrantFiled: May 10, 2018Date of Patent: August 18, 2020Assignee: Micron Technology, Inc.Inventors: Michael V. Ho, Ravi Kiran Kandikonda
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Patent number: 10747693Abstract: A memory device includes a first set of data input/output (I/O) devices configured to communicate a first portion of a data unit to or from an external controller; a second set of data I/O devices configured to communicate a second portion of the data unit to or from the external controller; a data control circuit can share the internal global data lines by multiplexing the timings of the first and second sets of data I/O devices, the data control circuit configured to route the data unit according to a data operation corresponding to the data unit; and a shared data bus coupling both the first set of data I/O devices and the second set of data I/O devices to the data control circuit, the shared data bus configured to relay both the first portion and the second portion of the data unit.Type: GrantFiled: May 10, 2018Date of Patent: August 18, 2020Assignee: Micron Technology, Inc.Inventors: Michael V. Ho, Ravi Kiran Kandikonda
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Publication number: 20200133525Abstract: A memory device includes a data path having a data bus. The memory derive further includes a first one-hot communications interface communicatively coupled to the data bus, and a second one-hot communications interface communicatively coupled to the data bus. The memory device additionally includes at least one memory bank, and an input/output (I/O) interface communicatively coupled to the at least one memory bank via the first one-hot communications interface and the second one-hot communications interface, wherein the first one-hot communications interface is configured to convert a first data pattern received by the I/O interface into one-hot signals transmitted via the data bus to the second one-hot communications interface, and wherein the second one-hot communications interface is configured to convert the one-hot signals into the first data pattern to be stored in the at least one memory bank.Type: ApplicationFiled: December 30, 2019Publication date: April 30, 2020Inventor: Ravi Kiran Kandikonda
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Patent number: 10552066Abstract: A memory device includes a data path having a data bus. The memory device further includes a first one-hot communications interface communicatively coupled to the data bus, and a second one-hot communications interface communicatively coupled to the data bus. The memory device additionally includes at least one memory bank, and an input/output (I/O) interface communicatively coupled to the at least one memory bank via the first one-hot communications interface and the second one-hot communications interface, wherein the first one-hot communications interface is configured to convert a first data pattern received by the I/O interface into one-hot signals transmitted via the data bus to the second one-hot communications interface, and wherein the second one-hot communications interface is configured to convert the one-hot signals into the first data pattern to be stored in the at least one memory bank.Type: GrantFiled: August 31, 2017Date of Patent: February 4, 2020Assignee: Micron Technology, Inc.Inventor: Ravi Kiran Kandikonda
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Publication number: 20190347042Abstract: A dynamic random-access memory (DRAM) device includes memory banks configured to store data and provide access to the stored data; and a data control circuit coupled to the memory banks, the data control circuit configured to: determine a pointer based on a received command, wherein the pointer corresponds to a target memory bank associated with the received command, and route a set of bits to or from the target memory bank using the pointer. In the long burst length and page mode operations where the array access is targeted in certain Bank Group, the pointer is generated and then allow the groups of data bits flowing through the center freely. This pseudo flow through scheme is low power and fast speed by removing the control of gating commands at each stage of the data path during Read and Write operations.Type: ApplicationFiled: May 10, 2018Publication date: November 14, 2019Inventors: Michael V. Ho, Ravi Kiran Kandikonda
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Publication number: 20190347223Abstract: A memory device includes a first set of data input/output (I/O) devices configured to communicate a first portion of a data unit to or from an external controller; a second set of data I/O devices configured to communicate a second portion of the data unit to or from the external controller; a data control circuit can share the internal global data lines by multiplexing the timings of the first and second sets of data I/O devices, the data control circuit configured to route the data unit according to a data operation corresponding to the data unit; and a shared data bus coupling both the first set of data I/O devices and the second set of data I/O devices to the data control circuit, the shared data bus configured to relay both the first portion and the second portion of the data unit.Type: ApplicationFiled: May 10, 2018Publication date: November 14, 2019Inventors: Michael V. Ho, Ravi Kiran Kandikonda
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Publication number: 20190348105Abstract: Aspects of the present disclosure eliminating the need for a memory device to have both a shifter that shifts input pin values from an input domain into a parity domain and another shifter that shifts a decoded command from the input domain into the parity domain. A memory device can achieve this by, when parity is being performed, shifting the input from the input pins into the parity domain prior to decoding the command. Using a multiplexer, the decoder can receive the command pin portion of the shifted input when parity checking is being performed and can receive the un-shifted command pin input when parity checking is not being performed. The decoder can use the command pin portion of the shifted input to generate shifted and decoded commands or can use the un-shifted command pin input to generate decoded commands.Type: ApplicationFiled: May 18, 2019Publication date: November 14, 2019Inventors: Jason M. Brown, Vijayakrishna J. Vankayala, William C. Waldrop, Kallol Mazumder, Byung S. Moon, Ravi Kiran Kandikonda
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Patent number: 10403353Abstract: Devices, systems, and methods for reducing noise couplings between propagation lines for size efficiency. In one embodiment, a memory device is provided, comprising a memory array and an input/output (I/O) circuit. The I/O circuit can include a first plurality of global data lines and a second plurality of global data lines. The second plurality of global data lines are directly interleaved between the first plurality of global date lines and are configured to shield the first plurality of global data lines. In some embodiments, the first plurality of global data lines are shorter in length than the second plurality of global data lines and are switched before the second plurality of global data lines are switched.Type: GrantFiled: May 10, 2018Date of Patent: September 3, 2019Assignee: Micron Technology, Inc.Inventors: Michael V. Ho, Ravi Kiran Kandikonda
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Patent number: 10354717Abstract: Aspects of the present disclosure eliminating the need for a memory device to have both a shifter that shifts input pin values from an input domain into a parity domain and another shifter that shifts a decoded command from the input domain into the parity domain. A memory device can achieve this by, when parity is being performed, shifting the input from the input pins into the parity domain prior to decoding the command. Using a multiplexer, the decoder can receive the command pin portion of the shifted input when parity checking is being performed and can receive the un-shifted command pin input when parity checking is not being performed. The decoder can use the command pin portion of the shifted input to generate shifted and decoded commands or can use the un-shifted command pin input to generate decoded commands.Type: GrantFiled: May 10, 2018Date of Patent: July 16, 2019Assignee: Micron Technology, Inc.Inventors: Jason M. Brown, Vijayakrishna J. Vankayala, William C. Waldrop, Kallol Mazumder, Byung S. Moon, Ravi Kiran Kandikonda
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Publication number: 20190065090Abstract: A memory device includes a data path having a data bus. The memory derive further includes a first one-hot communications interface communicatively coupled to the data bus, and a second one-hot communications interface communicatively coupled to the data bus. The memory device additionally includes at least one memory bank, and an input/output (I/O) interface communicatively coupled to the at least one memory bank via the first one-hot communications interface and the second one-hot communications interface, wherein the first one-hot communications interface is configured to convert a first data pattern received by the I/O interface into one-hot signals transmitted via the data bus to the second one-hot communications interface, and wherein the second one-hot communications interface is configured to convert the one-hot signals into the first data pattern to be stored in the at least one memory bank.Type: ApplicationFiled: August 31, 2017Publication date: February 28, 2019Inventor: Ravi Kiran Kandikonda