Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

Abstract: An apparatus for influencing process scheduling in a data processing system capable of utilizing a virtual memory processing scheme is disclosed. The data processing system includes multiple processing units. The processing units have volatile cache memories operating in a virtual address space that is greater than a real address space. The processing units and the respective volatile memories are coupled to a storage controller operating in a physical address space that is equal to the virtual address space. The processing units and the storage controller are coupled to a hard disk via an interconnect. The storage controller, which is coupled to a physical memory cache, allows the mapping of a virtual address from one of the volatile cache memories to a physical disk address directed to a storage location within the hard disk without transitioning through a real address. The physical memory cache contains a subset of information within the hard disk.

Abstract: A data processing system having no system memory is disclosed. The data processing system includes multiple processing units. The processing units have volatile cache memories operating in a virtual address space that is greater than a real address space. The processing units and the respective volatile memories are coupled to a storage controller operating in a physical address space that is equal to the virtual address space. The processing units and the storage controller are coupled to a hard disk via an interconnect. The storage controller, which is coupled to a physical memory cache, allows the mapping of a virtual address from one of the volatile cache memories to a physical disk address directed to a storage location within the hard disk without transitioning through a real address. The physical memory cache contains a subset of information within the hard disk.

Abstract: A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

Abstract: An access request for a data processing system having no system memory is disclosed. The data processing system includes multiple processing units. The processing units have volatile cache memories operating in a virtual address space that is greater than a real address space. The processing units and the respective volatile memories are coupled to a storage controller operating in a physical address space that is equal to the virtual address space. The processing units and the storage controller are coupled to a hard disk via an interconnect. The storage controller, which is coupled to a physical memory cache, allows the mapping of a virtual address from one of the volatile cache memories to a physical disk address directed to a storage location within the hard disk without transitioning through a real address. The physical memory cache contains a subset of information within the hard disk.

Abstract: A processor chip that provides a dynamically selectable operating mode in which particular sequences of instructions are executed without an external interrupt. The processor chip comprises an architected bit that may be set by software and which enables the external interrupt of the processing system to be dynamically enabled/disabled. When a sequence of instructions constituting a data move operation is being issued, the architected bit is toggled to an interrupt disabled state so that execution of the sequence of instructions occurs without an external interrupt. Following the execution of the sequence of instructions, the architected bit is toggled to an interrupt enabled state, which causes instruction execution to be subjected to external interrupts.

Abstract: A method and system are disclosed for running a manufacturing-level test program on an installed processor by interrupting processor execution of a non-test process. Periodic execution of the manufacturing-level test program allows the processor to continually self-test during normal function operation, in order to facilitate proper maintenance and function of the processor and a data processing system of which the processor is a part.

Abstract: A method and system are disclosed for predicting, based on historical information, a second level interrupt handler (SLIH) to service an interrupt. The predicted SLIH is speculatively executed concurrently with a first level interrupt handler (FLIH), which determines the correct SLIH for the interrupt. If the predicted SLIH has been correctly predicted, execution of the SLIH called by the FLIH is discontinued, and the predicted SLIH completes execution. If the predicted SLIH is mispredicted, then the execution of the predicted SLIH is discontinued, and the SLIH called by the FLIH continues to completion.

Abstract: A method and system are disclosed for managing saved process states in a memory of a data processing system that has multiple partitions executing independent operating systems. A hypervisor manager affords access to any processor in the data processing system for the purpose of storing process states for that processor to the memory, independent of the operating system running on the processor.

Abstract: A method for avoiding livelock within a multiprocessor data processing system when there are multiple, concurrent clone operations to similar memory data locations within a data processing system. A set of tokens are defined within the memory cloner for use prior to conducting a clone operation on the fabric. The tokens include a source token and a destination token. The tokens are issued on the fabric by a memory cloner prior to initiating the data clone operation. The tokens discover the availability of a source address and a destination address required to complete the clone operation. Once the response to the destination address token indicates that the destination address is not currently being utilized by another memory cloner to conduct another data clone operation, the memory cloner may issue the commands to initiate the memory clone operation.

Abstract: A processing state that enables a processor to resume processing operations before completion of a processor-issued data move operation. The processor executes instructions specifying a data clone operation and delays subsequent instruction execution while waiting for a receipt of an indication that the data clone operation has completed. In response to the instructions, a memory cloner issues a series of naked write operations targeting the destination memory location and tracks receipt of Null responses for each of the naked write operations. When a Null response has been received for each of the naked write operations, the memory cloner transmits an acknowledgment to the processor indicating that the write operation is architecturally complete before the actual data move has completed. In response to receiving the acknowledgment, the processor resumes execution of subsequent instructions in the instruction stream.

Abstract: A processor chip with a high speed memory cloner that enables movement of data directly from one memory location (of a data processing system) to another without the data having to be routed through the processor. The memory cloner includes processing logic that enables the release of the processor to continue processing other operations while the data are physically moved in the background. The memory cloner generates a sequence of naked writes (i.e., write operations with no data tenure) from the write data commands and forwards the naked writes to the memory controller of the destination memory module. When all the naked write operations receive a Null response (i.e., a response indicating that the specific addressed at the memory module are reserved/set to receive data), the memory cloner signals the processor that the move request is completed.

Abstract: A method and system are disclosed for managing a hard architected state of a processor that is critical for executing a process in the processor. A shadow copy of the hard architected state is stored from the processor to memory when an interrupt is received by the processor. The shadow copy of the hard architected permits rapid saving of the hard architected state for the interrupted process, so that the architected state of a next process can be immediately stored in the processor.

Abstract: A data processing system that includes a mode/reserve bit utilized to dynamically change a processor's operating mode between a virtual addressing mode and a real addressing mode. Each address block includes a reserve bit that indicates whether real or virtual addressing is desired, and the reserve bit is assigned a value by the software application executing on the processor. The value of the reserve bit is dynamically set and signals the processor which operating mode is required for the particular address block. The selection of virtual or real addressing mode is determined by the particular application that is being executed by the processor. When the particular application process seeks increased performance rather than protection, the virtual operating mode is selected, allowing the application process to send the effective addresses directly to the OS and hypervisor. This is accomplished by setting the reserve bit to the value for virtual addressing mode.

Abstract: A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.

Abstract: A method and system are disclosed for managing stored soft state information, such as the contents of cache memory and address translation information that are non-critical for executing a process within a processor. The soft states of idle processes are stored in system memory in virtual caches. Cache coherency of the soft states is maintained by snooping kill-type operations against the virtual caches in system memory.

Abstract: Disclosed is a data processing system that completes a data clone operation by routing the directly from a source location within said memory subsystem to a destination location within said memory subsystem. The data is not routed through the processor that initiated the data clone operation. The various storage components of the memory subsystem are directly interconnected to each other via a switch. The switch provides a large bandwidth for routing data. When a data clone operation is issued by the processor on the fabric of the data processing system, the data read operation sent to said source address is modified to include the destination address in place of the processor address. The switch routes the data to the address provided within the data read operation. Thus, the switch automatically routes the data to the destination address rather than to the processor address.

Abstract: A method for reserving memory buffers for receiving data prior to the actual movement of data on a data processing system. A naked write operation is generated that includes a destination address and an address of the processor generating the write operation. The naked write operation is then issued on the fabric of said data processing system without any accompanying data. The naked write operation is snooped by the memory controller associated with the destination address. The memory controller then provides a response that is sent to the processor. The response sent depends on whether the memory controller is able to allocate a buffer to the naked write operation. When the memory controller is able to allocate a buffer to the naked write operation, the memory controller issues a Null response, which triggers a read operation that sends the corresponding data to the buffer at a later time.

Abstract: A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.

Abstract: A data processing system comprising a coherency protocol that indicates and updates a coherency state of all data lines within said memory subsystem, and responsive to a naked write operation to a memory location containing a modified copy of data, changes the coherency state of the memory location from modified (M) to invalid (I) without initiating a push of the data to a corresponding address location of main memory. Included within the coherency protocol are specific group of responses for dealing with a naked write request that is received at a memory controller. These responses include: (1) issuing a retry response when the memory controller is unable to allocate a buffer for the write data operation and data at said memory location is not in an M state; (2) issuing a Null response when the memory controller is able to allocate the buffer; and (3) issuing a combined Ack_Resend response when the data at the memory location transitions from an M state to an I state.