Abstract: A system comprising processing circuitry a memory storing instructions that cause the system to detect a code change to source code included in a code repository, identify a relationship between the code change and an associated product feature, determine one or more dependent product features impacted by the code change, select a set of test cases including a subset of test cases related to the associated product feature and a subset of test cases related to the one or more dependent product features, execute the set of test cases, and update the code-to-feature mapping using results of executing the set of test case.

Abstract: Systems and methods include determination of a plurality of instances of a master configuration file, association of each of the plurality of instances with a first respective record of a first database table and with a second respective record of a second database table to determine a plurality of composite data records, determination of correlated features of the master configuration file, the first database table and the second database table based on the plurality of composite data records, and training of a machine learning model based on data of the correlated features of the master configuration file, the first database table and the second database table.

Abstract: A circuit includes, in part, a first transistor receiving a first clock signal at its gate, a second transistor receiving a second clock signal at its gate, a first impedance coupled to the drain terminal of the first transistor, a second impedance coupled to the drain terminal of the second transistor, a current source coupled to the source terminals of the first and second transistors, a third transistor receiving a third clock signal at its gate, a fourth transistor receiving a fourth clock signal at its gate, a fifth transistor coupling the drain terminal of the third transistor to the second impedance in response to a first control signal, a sixth transistor coupling the drain terminal of the fourth transistor to the second impedance in response to a second control signal, and a first variable current source coupled to the source terminals of the third and fourth transistors.

Abstract: A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

Abstract: A system for clock calibration is described herein which comprises a serializer configured to convert an input data stream in parallel format to provide an out data stream in a serial format; a clock source configured to generate one or more clock signals; a first frequency divider configured to provide at least one divided clock signal of the one or more clock signals; a delay line configured to delay at least one divided clock signal; and a clock calibrator configured to control delay of the at least one divided clock signal at the delay line to adjust the one or more divided clock signals at a fixed relationship with respect to the one or more clock signals based on voltage and temperature variation.

Abstract: A clock and data recovery (CDR) circuit includes first through ninth samplers, a clock recovery circuit, a level finding circuit, an offset voltage generator, and a data recovery circuit. Each of the first through ninth samplers samples a data signal based on one of first through ninth reference offset voltage levels to generate first through ninth intermediate signals, respectively. The clock recovery circuit generates the first through fourth clock signals based on the first, second, fifth, and eighth intermediate signals. The level finding circuit generates a band level signal by varying the third intermediate signal. The offset voltage generator generates one of: the fourth and seventh reference offset voltage levels, the fifth and eighth reference offset voltage levels, and the sixth and ninth reference offset voltage levels based on the band level signal. The data recovery circuit detects an output data signal based on the fourth through ninth intermediate signals.

Abstract: A clock and data recovery circuit includes a bang-bang phase detector (BBPD), a voltage controlled oscillator (VCO), a frequency control circuit, and an up-down counter. The BBPD generates an early-late signal by determining whether serialized data received by the BBPD is early or late with respect to a VCO clock signal generated by the VCO. A phase of the VCO clock signal is controlled based on the early-late signal. The frequency control circuit compares a frequency of the VCO clock signal and a target frequency and generates an up/down signal. Based on the up/down signal, the up-down counter increments or decrements the frequency of the VCO clock signal to match the target frequency.

Abstract: A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

Abstract: A system for clock calibration is described herein which comprises a serializer configured to convert an input data stream in parallel format to provide an out data stream in a serial format; a clock source configured to generate one or more clock signals; a first frequency divider configured to provide at least one divided clock signal of the one or more clock signals; a delay line configured to delay at least one divided clock signal; and a clock calibrator configured to control delay of the at least one divided clock signal at the delay line to adjust the one or more divided clock signals at a fixed relationship with respect to the one or more clock signals based on voltage and temperature variation.

Abstract: A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

Abstract: A clock and data recovery (CDR) circuit receives a data signal and generates a clock signal and a recovered data signal. The CDR circuit includes a clock-recovery circuit (CRC), a sampling phase-recovery circuit (PRC), an analog-to-digital converter (ADC), and a data-recovery circuit (DRC). The CRC receives the data signal and generates an intermediate clock signal. The PRC receives the intermediate clock signal, a sampled data signal and the recovered data signal, and generates the clock signal. The ADC receives the data signal and generates the sampled data signal. The DRC receives the sampled data signal and generates the recovered data signal. The clock signal is phase and frequency synchronized with the data signal.

Abstract: A clock and data recovery (CDR) circuit receives a data signal and generates a clock signal and a recovered data signal. The CDR circuit includes a clock-recovery circuit (CRC), a sampling phase-recovery circuit (PRC), an analog-to-digital converter (ADC), and a data-recovery circuit (DRC). The CRC receives the data signal and generates an intermediate clock signal. The PRC receives the intermediate clock signal, a sampled data signal and the recovered data signal, and generates the clock signal. The ADC receives the data signal and generates the sampled data signal. The DRC receives the sampled data signal and generates the recovered data signal. The clock signal is phase and frequency synchronized with the data signal.

Abstract: A clock and data recovery circuit includes a bang-bang phase detector (BBPD), a voltage controlled oscillator (VCO), a frequency control circuit, and an up-down counter. The BBPD generates an early-late signal by determining whether serialized data received by the BBPD is early or late with respect to a VCO clock signal generated by the VCO. A phase of the VCO clock signal is controlled based on the early-late signal. The frequency control circuit compares a frequency of the VCO clock signal and a target frequency and generates an up/down signal. Based on the up/down signal, the up-down counter increments or decrements the frequency of the VCO clock signal to match the target frequency.

Abstract: A lock time measurement system to determine a lock time includes a measurement device, a serializer-deserializer (SERDES), a pattern generator, and a splitter. In a first mode, the SERDES receives first data from the pattern generator by way of the splitter. A receiver of the SERDES outputs a recovered clock signal based on the first data to a transmitter. The transmitter includes a serializer and a multiplexer. The serializer receives the recovered clock signal by way of the multiplexer and modifies second data based on the recovered clock signal and outputs serial data. A measurement device, connected to the transmitter and the splitter determines the lock time. In a second mode, the SERDES functions as a transmitter for transmitting data and a receiver for receiving data in a communication link. The system has a better accuracy and utilizes existing receiver and driver circuits.

Abstract: A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

Abstract: A high gain differential amplifier includes first through eighth transistors, first through third degeneration resistors, and first through third current sources. The fourth and fifth transistors form a p-type metal-oxide-semiconductor (PMOS) transistor pair. Further, the second and eighth transistors form a current mirror circuit. The PMOS transistor pair and the current mirror circuit form a common mode feedback circuit. The high gain differential amplifier controls the common-mode output voltage with the common mode feedback circuit and a reference voltage.

Abstract: A lock time measurement system to determine a lock time includes a measurement device, a serializer-deserializer (SERDES), a pattern generator, and a splitter. In a first mode, the SERDES receives first data from the pattern generator by way of the splitter. A receiver of the SERDES outputs a recovered clock signal based on the first data to a transmitter. The transmitter includes a serializer and a multiplexer. The serializer receives the recovered clock signal by way of the multiplexer and modifies second data based on the recovered clock signal and outputs serial data. A measurement device, connected to the transmitter and the splitter determines the lock time. In a second mode, the SERDES functions as a transmitter for transmitting data and a receiver for receiving data in a communication link. The system has a better accuracy and utilizes existing receiver and driver circuits.

Abstract: A duty cycle correction (DCC) circuit includes first and second pluralities of logic gates, a low pass filter, an error amplifier, and a differential amplifier. The DCC circuit receives first and second clock signals from the VCO. The first and second pluralities of logic gates receive first and second superimposed clock signals and generate first and second output clock signals, respectively. The error amplifier rectifies a common error of the first and second output clock signals, and generates a common mode error voltage signal. The differential amplifier generates first and second error signals based on the common mode error voltage signal. The first and second error signals converge the duty cycles of the first and second output clock signals to a 50% duty cycle.

Abstract: A driver circuit includes a first inverter, a bias-control circuit, and a second inverter. The first inverter, which is connected between a first supply voltage and ground, receives an input data signal and generates an inverted version of the input data signal. The bias-control circuit, which is connected between a second supply voltage and the first inverter, receives the inverted version of the input data signal and a bias signal, and generates a level-shifted data signal based on the inverted version of the input data signal, the bias signal, and the second supply voltage. The bias-control circuit reduces a difference between voltage levels of the second supply voltage and the inverted version of the input data signal. The second inverter is connected between the second supply voltage and ground, and further connected to the bias-control circuit and first inverter and generates an output data signal.

Abstract: A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.