Abstract: A physical layer transceiver for a node in a wireline communication system includes receiver circuitry for receiving communications from a link partner on a first link path, transmitter circuitry for transmitting communications to the link partner on a second link path, and an energy-efficient Ethernet (EEE) controller for reducing power consumption on the first or second link path, when activity on that link path is reduced. In a low-power mode, there are periodic refresh intervals of a first duration, during which signals are received or transmitted, and, between the refresh intervals, quiet intervals of a second, longer, duration, during which transmission and reception of signals are avoided. The EEE controller detects a change in an environmental condition affecting that link path, and upon detection of that change, adjusts a parameter of the low-power mode on at least one of the first and second link paths.

Abstract: A device may store a credit value for each of multiple output components. The device may receive packets from a network device via an input component. The device may cause the input component to queue the packets. The device may selectively dequeue a packet from the input component, to be sent to an output component, based on whether the credit value for the output component satisfies a credit threshold. The device may send the packet to the output component based on a destination of the packet when the packet is dequeued from the input component. The device may determine a size of the packet after the packet is dequeued. The device may update the credit value for the output component based on the size of the packet. The device may output the packet to another network device via the output component.

Abstract: A device may store a credit value for each of multiple output components. The device may receive packets from a network device via an input component. The device may cause the input component to queue the packets. The device may selectively dequeue a packet from the input component, to be sent to an output component, based on whether the credit value for the output component satisfies a credit threshold. The device may send the packet to the output component based on a destination of the packet when the packet is dequeued from the input component. The device may determine a size of the packet after the packet is dequeued. The device may update the credit value for the output component based on the size of the packet. The device may output the packet to another network device via the output component.

Abstract: A device may store a credit value for each of multiple output components. The device may receive packets from a network device via an input component. The device may cause the input component to queue the packets. The device may selectively dequeue a packet from the input component, to be sent to an output component, based on whether the credit value for the output component satisfies a credit threshold. The device may send the packet to the output component based on a destination of the packet when the packet is dequeued from the input component. The device may determine a size of the packet after the packet is dequeued. The device may update the credit value for the output component based on the size of the packet. The device may output the packet to another network device via the output component.

Abstract: A communication device may include a cyclic redundancy check (CRC) calculator. The CRC calculator may determine a packet remainder of a packet based on a data path width associated with the communication device; append zeros to the packet remainder to generate an appended packet remainder equal in size to the data path width; compute a first CRC value for the appended packet; reverse bits of the computed first CRC value to obtain a reversed CRC value; multiply the bit reversed CRC value with a value based on a reciprocal CRC polynomial to generate a multiplication product; compute a second CRC value for the generated multiplication product based on the reciprocal CRC polynomial; and reverse bits of the second CRC value to generate a CRC for the packet.

Abstract: Techniques relate to the regeneration of a cyclical redundancy check (CRC) value of a data packet in a manner that avoids a complete CRC recomputation based on the entire packet after only a portion of a packet has been modified. When modifying and forwarding a packet, a network device identifies only the changed portions of a packet and computes an updated CRC for the packet based on the original CRC, the modified portions, and the length from the modified field to end of packet.

Abstract: A method, arithmetic divider unit, and system are disclosed for dividing a dividend DZM . . . Z0 having a most significant bit ZM and a plurality of less significant bits ZM?1 through Z0 by a divisor RZN . . . Z0 having a most significant bit ZN and a plurality of less significant bits ZN?1 through Z0. The method, arithmetic divisor unit, and system round the divisor to the next significant bit greater than the divisor's most significant bit ZN to produce a first partial divisor RZN+1, divide the dividend DZM . . . Z0 by the first partial divisor RZN+1 to produce a first partial quotient QN, calculate one or more additional partial quotients based on one or more divisor bits selected from the plurality of divisor bits ZN?1 through Z0, and add the first partial quotient QN and one or more additional partial quotients to produce an estimated final quotient.

Abstract: A method for designing a read-only memory (ROM), and related device, includes partitioning a dataset into two or more sub-datasets that each have the same address space, but are of a smaller bit-width than the original dataset. The sub-datasets are row collapsed, and then respective memory cells for the sub-datasets are provided. The output of the memory cells provides the output of the ROM. Each memory cell includes a decoder that maps addresses to word lines based on mapping information obtained during row collapsing, and a logic array driven by the decoder that encodes the data words of the sub-dataset.

Abstract: A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data word are mapped by the decoder to the same address decode line. Each address decode line is electrically connected to a bit output line as determined by the data set. An initial design of the ROM uses N connecting devices to respectively electrically connect N of the address decode lines to a bit output line. If N exceeds X/2, then an optimization process is performed. The optimization process involves electrically disconnecting each address decode line that was connected to the bit output line, and electrically connecting each address decode line that was not connected to the bit output line. The output of the bit output line is then run through a logical inverter to provide the correct output data bit.

Abstract: A method for designing a read-only memory (ROM), and related device, includes partitioning a dataset into two or more sub-datasets that each have the same address space, but are of a smaller bit-width than the original dataset. The sub-datasets are row collapsed, and then respective memory cells for the sub-datasets are provided. The output of the memory cells provides the output of the ROM. Each memory cell includes a decoder that maps addresses to word lines based on mapping information obtained during row collapsing, and a logic array driven by the decoder that encodes the data words of the sub-dataset.

Abstract: A method for designing a read-only memory (ROM), and related device, includes partitioning a dataset into two or more sub-datasets that each have the same address space, but are of a smaller bit-width than the original dataset. The sub-datasets are row collapsed, and then respective memory cells for the sub-datasets are provided. The output of the memory cells provides the output of the ROM. Each memory cell includes a decoder that maps addresses to word lines based on mapping information obtained during row collapsing, and a logic array driven by the decoder that encodes the data words of the sub-dataset.

Abstract: The invention provides a method, arithmetic divider unit, and system for dividing a dividend DZm . . . Z0 having a most significant bit and a plurality of less significant bits by a divisor having a most significant bit ZN and a plurality of less significant bits ZN?1 through Z0. The method, arithmetic divider unit, and system round the divisor to the next significant bit greater than the divisor's most significant bit ZN to produce a first partial divisor RZN, divide the dividend DZm . . . Z0 by the first partial divisor RZN to produce a first partial quotient QN, calculate one or more additional partial quotients based on one or more divisor bits selected from the plurality of divisor bits ZN?1 through Z0, and add the first partial quotient QN and one or more additional partial quotients to produce an estimated final quotient.

Abstract: A method for designing a read-only memory (ROM), and related device, includes partitioning a dataset into two or more sub-datasets that each have the same address space, but are of a smaller bit-width than the original dataset. The sub-datasets are row collapsed, and then respective memory cells for the sub-datasets are provided. The output of the memory cells provides the output of the ROM. Each memory cell includes a decoder that maps addresses to word lines based on mapping information obtained during row collapsing, and a logic array driven by the decoder that encodes the data words of the sub-dataset.

Abstract: A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data word are mapped by the decoder to the same address decode line. Each address decode line is electrically connected to a bit output line as determined by the data set. An initial design of the ROM uses N connecting devices to respectively electrically connect N of the address decode lines to a bit output line. If N exceeds X/2, then an optimization process is performed. The optimization process involves electrically disconnecting each address decode line that was connected to the bit output line, and electrically connecting each address decode line that was not connected to the bit output line. The output of the bit output line is then run through a logical inverter to provide the correct output data bit.