Patents by Inventor Ravi Rajagopalan
Ravi Rajagopalan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220257570Abstract: Methods of treating neurological diseases and disorders associated with protein aggregation using calpain inhibitors are provided. Said neurological diseases associated with protein aggregation include polyglutamine expansion diseases such as Huntington's disease, Machado-Joseph disease, and spinocerebellar ataxias.Type: ApplicationFiled: July 28, 2020Publication date: August 18, 2022Inventors: Prabha Ibrahim, Maria Fuentes, P. T. Ravi Rajagopalan, Walter Yu
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Patent number: 11061822Abstract: A method, apparatus, and system for reducing pipeline stalls due to address translation misses is presented. An apparatus comprises a memory access instruction pipeline, a translation lookaside buffer coupled to the memory access instruction pipeline, and a TLB miss queue coupled to both the TLB and the memory access instruction pipeline. The TLB miss queue is configured to selectively store a first memory access instruction that has been removed from the memory access instruction pipeline as a result of the first memory access instruction missing in the TLB along with information associated with the first memory access instruction. The TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline associated with a return of an address translation related to the first memory access instruction.Type: GrantFiled: August 27, 2018Date of Patent: July 13, 2021Assignee: Qualcomm IncorporatedInventors: Pritha Ghoshal, Niket Choudhary, Ravi Rajagopalan, Patrick Eibl, Brian Stempel, David Scott Ray, Thomas Philip Speier
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Publication number: 20210113560Abstract: Disclosed herein are methods of treating fibrotic disorders by administering compounds selective for CAPN1, CAPN2, and/or CAPN9 such that side effects, off pathway interactions, and/or toxicities are minimized Such methods may, for example, minimize unintended effects of therapeutic compounds by providing dosing and dosage forms that minimize the level of unbound drug within the relevant tissues of a patient undergoing treatment.Type: ApplicationFiled: March 25, 2019Publication date: April 22, 2021Inventors: Brad Owen Buckman, Prabha Ibrahim, P T Ravi Rajagopalan
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Patent number: 10811257Abstract: A method may include depositing a carbon layer on a substrate using physical vapor deposition, wherein the carbon layer exhibits compressive stress, and is characterized by a first stress value; and directing a dose of low-mass species into the carbon layer, wherein, after the directing, the carbon layer exhibits a second stress value, less compressive than the first stress value.Type: GrantFiled: June 4, 2018Date of Patent: October 20, 2020Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Rajesh Prasad, Tzu-Yu Liu, Kyu-Ha Shim, Tom Ho Wing Yu, Zhong Qiang Hua, Adolph Miller Allen, Viabhav Soni, Ravi Rajagopalan, Nobuyuki Sasaki
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Publication number: 20200065260Abstract: A method, apparatus, and system for reducing pipeline stalls due to address translation misses is presented. An apparatus comprises a memory access instruction pipeline, a translation lookaside buffer coupled to the memory access instruction pipeline, and a TLB miss queue coupled to both the TLB and the memory access instruction pipeline. The TLB miss queue is configured to selectively store a first memory access instruction that has been removed from the memory access instruction pipeline as a result of the first memory access instruction missing in the TLB along with information associated with the first memory access instruction. The TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline associated with a return of an address translation related to the first memory access instruction.Type: ApplicationFiled: August 27, 2018Publication date: February 27, 2020Inventors: Pritha GHOSHAL, Niket CHOUDHARY, Ravi RAJAGOPALAN, Patrick EIBL, Brian STEMPEL, David Scott Ray, Thomas Philip SPEIER
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Publication number: 20190304783Abstract: A method may include depositing a carbon layer on a substrate using physical vapor deposition, wherein the carbon layer exhibits compressive stress, and is characterized by a first stress value; and directing a dose of low-mass species into the carbon layer, wherein, after the directing, the carbon layer exhibits a second stress value, less compressive than the first stress value.Type: ApplicationFiled: June 4, 2018Publication date: October 3, 2019Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Rajesh Prasad, Tzu-Yu Liu, Kyu-HA Shim, Tom Ho Wing Yu, Zhong Qiang Hua, Adolph Miller Allen, Viabhav Soni, Ravi Rajagopalan, Nobuyuki Sasaki
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Patent number: 9807946Abstract: A vertical planter having a partitioned tray, a liner, and a sliding wire support grid, wherein the partitioned tray engages the sliding wire support grid to provide access to the partitioned tray.Type: GrantFiled: July 11, 2014Date of Patent: November 7, 2017Assignee: PRIDE GARDEN PRODUCTSInventor: Ravi Rajagopalan
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Publication number: 20150013223Abstract: A vertical planter having a partitioned tray, a liner, and a sliding wire support grid, wherein the partitioned tray engages the sliding wire support grid to provide access to the partitioned tray.Type: ApplicationFiled: July 11, 2014Publication date: January 15, 2015Inventor: Ravi Rajagopalan
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Patent number: 8499208Abstract: The content and order of a predetermined sequence of hard-coded and/or quasi-programmable test patterns may be altered during a Built-In Self-Test (BIST) routine. As such, knowledge gained post design completion may be reflected in the selection and arrangement of available tests to be executed during a BIST routine. In one embodiment, a sequence of hard-coded and/or quasi-programmable tests is executed during a BIST routine by receiving test ordering information for the sequence of tests and executing the sequence of tests in an order indicated by the test ordering information. A corresponding BIST circuit comprises a storage element and a state machine. The storage element is configured to store test ordering information for the sequence of tests. The state machine is configured to execute the sequence of tests in an order indicated by the test ordering information.Type: GrantFiled: October 27, 2006Date of Patent: July 30, 2013Assignee: QUALCOMM IncorporatedInventors: James Norris Dieffenderfer, Anand Krishnamurthy, Clint Wayne Mumford, Jason Lawrence Panavich, Ketan Vitthal Patel, Ravi Rajagopalan, Thomas Philip Speier
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Patent number: 8443162Abstract: Techniques for controllably allocating a portion of a plurality of memory banks as cache memory are disclosed. To this end, a configuration tracker and a bank selector are employed. The configuration tracker configures whether each memory bank is to operate in a cache or not. The bank selector has a plurality of bank distributing functions. Upon receiving an incoming address, the bank selector determines the configuration of memory banks currently operating as the cache and applies an appropriate bank distributing function based on the configuration of memory banks. The applied bank distributing function utilizes bits in the incoming address to access one of the banks configured as being in the cache.Type: GrantFiled: January 21, 2005Date of Patent: May 14, 2013Assignee: QUALCOMM IncorporatedInventors: Thomas Philip Speier, James Norris Dieffenderfer, Ravi Rajagopalan
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Publication number: 20120279123Abstract: An injection molded container such as a flower pot having an outer surface and an inner surface and an indentation of a shape and size corresponding to the shape and size of a design element member, the design element member and the container member adapted to easily engage one another and to be easily disengaged so as to provide at least one decorative element on the outside surface of the container which can be easily changed according to a selectable design scheme.Type: ApplicationFiled: May 5, 2011Publication date: November 8, 2012Applicant: Pride Garden ProductsInventor: Ravi Rajagopalan
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Patent number: 7745333Abstract: In one embodiment of the invention, a method for forming a tungsten-containing layer on a substrate is provided which includes positioning a substrate containing a barrier layer disposed thereon in a process chamber, exposing the substrate to a first soak process for a first time period and depositing a nucleation layer on the barrier layer by flowing a tungsten-containing precursor and a reductant into the process chamber. The method further includes exposing the nucleation layer to a second soak process for a second time period and depositing a bulk layer on the nucleation layer.Type: GrantFiled: July 24, 2008Date of Patent: June 29, 2010Assignee: Applied Materials, Inc.Inventors: Ken Kaung Lai, Ravi Rajagopalan, Amit Khandelwal, Madhu Moorthy, Srinivas Gandikota, Joseph Castro, Avgerinos V. Gelatos, Cheryl Knepfler, Ping Jian, Hongbin Fang, Chao-Ming Huang, Ming Xi, Michael X. Yang, Hua Chung, Jeong Soo Byun
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Patent number: 7621075Abstract: A liner for use in a horticultural planter contains an integral water tray which is located between inner and outer fibrous layers of a liner. The water tray extends from a bottom surface of the liner toward a peripheral top edge. An overflow region is included with the water tray near the peripheral top edge of the liner.Type: GrantFiled: July 30, 2004Date of Patent: November 24, 2009Assignee: The Pride Group, Inc.Inventor: Ravi Rajagopalan
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Publication number: 20090047246Abstract: The embodiments provide compounds of the general Formula I, as well as compositions, including pharmaceutical compositions, comprising a subject compound. The embodiments further provide treatment methods, including methods of treating a hepatitis C virus infection, the methods generally involving administering to an individual in need thereof an effective amount of a subject compound or composition.Type: ApplicationFiled: February 11, 2008Publication date: February 19, 2009Applicant: InterMune, Inc.Inventors: Leonid Beigelman, Brad Buckman, Vladimir Serebryany, Guangyi Wang, Jasenka Matulic-Adamic, Antitsa Dimitrova Stoycheva, Steven W. Andrews, Shawn Maurice Misialek, P.T. Ravi Rajagopalan, Andrew M. Fryer, Indrani Gunawardana, Julia Haas, Lily Huang, Machender R. Madduru, Gan Zhang, Karl Kossen, Scott D. Seiwert, Lawrence M. Blatt
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Publication number: 20080280438Abstract: In one embodiment of the invention, a method for forming a tungsten-containing layer on a substrate is provided which includes positioning a substrate containing a barrier layer disposed thereon in a process chamber, exposing the substrate to a first soak process for a first time period and depositing a nucleation layer on the barrier layer by flowing a tungsten-containing precursor and a reductant into the process chamber. The method further includes exposing the nucleation layer to a second soak process for a second time period and depositing a bulk layer on the nucleation layer.Type: ApplicationFiled: July 24, 2008Publication date: November 13, 2008Inventors: Ken Kaung Lai, Ravi Rajagopalan, Amit Khandelwal, Madhu Moorthy, Srinivas Gandikota, Joseph Castro, Aygerinos V. Gelatos, Cheryl Knepfler, Ping Jian, Hongbin Fang, Chao-Ming Huang, Ming Xi, Michael X. Yang, Hua Chung, Jeong Soo Byun
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Patent number: 7405158Abstract: In one embodiment of the invention, a method for forming a tungsten-containing layer on a substrate is provided which includes positioning a substrate containing a barrier layer disposed thereon in a process chamber, exposing the substrate to a first soak process for a first time period and depositing a nucleation layer on the barrier layer by flowing a tungsten-containing precursor and a reductant into the process chamber. The method further includes exposing the nucleation layer to a second soak process for a second time period and depositing a bulk layer on the nucleation layer.Type: GrantFiled: January 19, 2005Date of Patent: July 29, 2008Assignee: Applied Materials, Inc.Inventors: Ken Kaung Lai, Ravi Rajagopalan, Amit Khandelwal, Madhu Moorthy, Srinivas Gandikota, Joseph Castro, Averginos V. Gelatos, Cheryl Knepfler, Ping Jian, Hongbin Fang, Chao-Ming Huang, Ming Xi, Michael X. Yang, Hua Chung, Jeong Soo Byun
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Publication number: 20080115026Abstract: The content and order of a predetermined sequence of hard-coded and/or quasi-programmable test patterns may be altered during a Built-In Self-Test (BIST) routine. As such, knowledge gained post design completion may be reflected in the selection and arrangement of available tests to be executed during a BIST routine. In one embodiment, a sequence of hard-coded and/or quasi-programmable tests is executed during a BIST routine by receiving test ordering information for the sequence of tests and executing the sequence of tests in an order indicated by the test ordering information. A corresponding BIST circuit comprises a storage element and a state machine. The storage element is configured to store test ordering information for the sequence of tests. The state machine is configured to execute the sequence of tests in an order indicated by the test ordering information.Type: ApplicationFiled: October 27, 2006Publication date: May 15, 2008Inventors: James Norris Dieffenderfer, Anand Krishnamurthy, Clint Wayne Mumford, Jason Lawrence Panavich, Ketan Vitthal Patel, Ravi Rajagopalan, Thomas Philip Speier
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Publication number: 20060168390Abstract: Techniques for controllably allocating a portion of a plurality of memory banks as cache memory are disclosed. To this end, a configuration tracker and a bank selector are employed. The configuration tracker configures whether each memory bank is to operate in a cache or not. The bank selector has a plurality of bank distributing functions. Upon receiving an incoming address, the bank selector determines the configuration of memory banks currently operating as the cache and applies an appropriate bank distributing function based on the configuration of memory banks. The applied bank distributing function utilizes bits in the incoming address to access one of the banks configured as being in the cache.Type: ApplicationFiled: January 21, 2005Publication date: July 27, 2006Inventors: Thomas Speier, James Dieffenderfer, Ravi Rajagopalan
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Publication number: 20060009034Abstract: In one embodiment of the invention, a method for forming a tungsten-containing layer on a substrate is provided which includes positioning a substrate containing a barrier layer disposed thereon in a process chamber, exposing the substrate to a first soak process for a first time period and depositing a nucleation layer on the barrier layer by flowing a tungsten-containing precursor and a reductant into the process chamber. The method further includes exposing the nucleation layer to a second soak process for a second time period and depositing a bulk layer on the nucleation layer.Type: ApplicationFiled: January 19, 2005Publication date: January 12, 2006Inventors: Ken Lai, Ravi Rajagopalan, Amit Khandelwal, Madhu Moorthy, Srinivas Gandikota, Joseph Castro, Aygerinos Gelatos, Cheryl Knepfler, Ping Jian, Hongbin Fang, Chao-Ming Huang, Ming Xi, Michael Yang, Hua Chung, Jeong Byun
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Publication number: 20050011120Abstract: A liner for use in a horticultural planter contains an integral water tray which is located between inner and outer fibrous layers of a liner. The water tray extends from a bottom surface of the liner toward a peripheral top edge. The water tray is integral with the liner and located between outer and inner fibrous layers. An overflow region is included with the water tray near the peripheral top edge of the liner.Type: ApplicationFiled: July 30, 2004Publication date: January 20, 2005Inventor: Ravi Rajagopalan