Abstract: A device is provided for detecting temperature-induced delays in a combinational logic path. A signal at the output of the logic path is latched at a first latch using a primary clock signal. The primary clock signal is delayed by a delay element to provide a delayed clock signal. The output of the logic path is latched at a second latch using the delayed clock signal. The delay element delays the clock signal by an amount that indicates the occurrence of an over-temperature condition at the logic path. A comparator compares the data latched at the first latch to the data latched at the second latch and provides an error signal indicative of an over-temperature condition if the first and second latch contain different data values.

Abstract: A current-steering digital-to-analog converter (DAC) is tested using a test component having a relaxation oscillator with an oscillation frequency based on the output current of the DAC. A series of test values is provided in sequence to the DAC for conversion to an output current with a magnitude that varies with the test values. The test component counts the number of oscillations (“the oscillation count”) of the relaxation oscillator over a fixed duration that is substantially equal for each test value. As the number of oscillations over the fixed duration depends on the oscillation frequency of the relaxation oscillator, which in turn is based on the magnitude of the output current, the oscillation count can be used as a relative measure of the magnitude of the output current for the corresponding test value. Accordingly, the oscillation counts for the test values can be used to determine operational characteristics of the DAC.

Abstract: A current-steering digital-to-analog converter (DAC) is tested using a test component having a relaxation oscillator with an oscillation frequency based on the output current of the DAC. A series of test values is provided in sequence to the DAC for conversion to an output current with a magnitude that varies with the test values. The test component counts the number of oscillations (“the oscillation count”) of the relaxation oscillator over a fixed duration that is substantially equal for each test value. As the number of oscillations over the fixed duration depends on the oscillation frequency of the relaxation oscillator, which in turn is based on the magnitude of the output current, the oscillation count can be used as a relative measure of the magnitude of the output current for the corresponding test value. Accordingly, the oscillation counts for the test values can be used to determine operational characteristics of the DAC.

Abstract: A device is provided for detecting delays of data due to over-temperature conditions, the device includes a first latch having a data input and a clock input and an output, and a first delay path including combinational logic, a first input coupled to the output of the first latch, and an output. The device further includes a second latch having a data input coupled to the output of the first delay path, a clock input coupled to the clock input of first latch, and an output, and a delay element having a data input coupled to the clock input of the first latch and an output. The device includes a third latch having a data input coupled to the output of the first delay path, a clock input coupled to the output of the delay element, and an output, and a comparator having a first input coupled to the output of the second latch, a second input coupled to the output of the third latch, and an output.

Abstract: A memory system having multiple memory banks is configured to prevent bank conflict between access requests. The memory system includes a memory controller and a plurality of memory banks operatively coupled to the memory controller, with each of the memory banks configured for storing a plurality of data items. More particularly, a given data item is stored as multiple copies of the data item with the multiple copies being stored in respective ones of a designated minimum number of the memory banks. The memory controller is adapted to process requests for access to the data items stored in the memory banks in accordance with a specified bank access sequence.

Abstract: A method and system of memory management incorporates multiple banks of memory devices organized into independent channels wherein each bank of memory devices contains duplicate data. A tree memory controller controls data read and write accesses to each of the banks in each of the channels. A bank queue for each bank in each channel keeps track of bank availability. When read or write requests are received at the tree memory controller, the controller checks the availability of each bank in a channel, identifies a first available bank, and executes the read request from the first available bank. In response to a write request, the controller blocks all read requests once it has confirmed that data to be written is complete for the selected memory word length. As soon as each bank queue for read requests is empty, the controller initiates burst mode transfer of the completed data word to all banks concurrently.

Abstract: A process for fabricating a droplet plate for the printhead of an ink-jet printer, which process provides design flexibility, precise dimension control, as well as material robustness. Also provided is a droplet plate fabricated in accord with the process.

Abstract: A process for fabricating a droplet plate for the printhead of an ink-jet printer, which process provides design flexibility, precise dimension control, as well as material robustness. Also provided is a droplet plate fabricated in accord with the process.

Abstract: A process for fabricating a droplet plate for the printhead of an ink-jet printer, which process provides design flexibility, precise dimension control, as well as material robustness. Also provided is a droplet plate fabricated in accord with the process.

Abstract: A method and system of memory management incorporates multiple banks of memory devices organized into independent channels wherein each bank of memory devices contains duplicate data. A tree memory controller controls data read and write accesses to each of the banks in each of the channels. A bank queue for each bank in each channel keeps track of bank availability. When read or write requests are received at the tree memory controller, the controller checks the availability of each bank in a channel, identifies a first available bank, and executes the read request from the first available bank. In response to a write request, the controller blocks all read requests once it has confirmed that data to be written is complete for the selected memory word length. As soon as each bank queue for read requests is empty, the controller initiates burst mode transfer of the completed data word to all banks concurrently.

Abstract: A memory system having multiple memory banks is configured to prevent bank conflict between access requests. The memory system includes a memory controller and a plurality of memory banks operatively coupled to the memory controller, with each of the memory banks configured for storing a plurality of data items. More particularly, a given data item is stored as multiple copies of the data item with a given one of the multiple copies in each of a designated minimum number of the memory banks. The memory controller is adapted to process requests for access to the data items stored in the memory banks in accordance with a specified bank access sequence. The minimum number of memory banks for storage of the multiple copies of the given data item may be determined as a function of a random cycle time and a random bank access delay of the memory banks, e.g., as an integer greater than or equal to a ratio of the random cycle time to the random bank access delay.

Abstract: A process for fabricating a droplet plate for the printhead of an inkjet printer, which process provides design flexibility, precise dimension control, as well as material robustness. Also provided is a droplet plate fabricated in accord with the process.

Abstract: A process for fabricating a droplet plate for the printhead of an ink-jet printer, which process provides design flexibility, precise dimension control, as well as material robustness. Also provided is a droplet plate fabricated in accord with the process.

Abstract: A highly-efficient thermal inkjet printhead. The printhead includes a primary layer of polycrystalline silicon (preferably doped) having at least one portion thereof which functions as an ink expulsion resistor. Positioned over and above the primary layer is a secondary layer of material having at least one section produced from a selected metal silicide compound and at least another section fabricated from undoped polycrystalline silicon. The metal silicide-containing section functions as an interconnect structure and is operatively connected to the resistor in the primary layer (which is positioned beneath the secondary layer). The undoped polycrystalline silicon section is at least partially aligned over and above the resistor. As a result, the resistor is “buried” beneath the secondary layer and the various portions thereof. This system provides improved reliability, greater dimensional simplicity, optimized electrical/thermal properties, and superior versatility.

Abstract: A highly-efficient thermal inkjet printhead. The printhead includes at least one doped polycrystalline silicon resistor which communicates with an external signal source using a unique interconnection system. Specifically, a primary layer of electrically conductive material (optimally a metal silicide) is connected to the resistor. An additional layer of electrically conductive material is attached to and above the primary layer. The additional layer terminates at a position which is spaced outwardly and apart from the resistor to form a gap therebetween. However, the underlying primary layer electrically links the additional layer to the resistor. Alternatively, a dielectric layer is attached to and above the primary layer, with the additional layer being secured to the dielectric layer. At least one electrically conductive contact member is provided within the dielectric layer to link the primary and additional layers.