Abstract: One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a substrate, the substrate having a core region and a periphery region; a charge trapping dielectric over the core region of the substrate; a gate dielectric in the periphery region of the substrate; buried bitlines under the charge trapping dielectric in the core region; and wordlines over the charge trapping dielectric in the core region, wherein the core region is substantially planar.

Abstract: A method of erasing a memory cell with a substrate that has a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains an initial amount of charge. The method includes applying a constant first voltage across the gate and applying a second constant voltage across said the region. A third constant voltage is applied in a region of the substrate outside of the first and second regions so that a first portion of the first amount of charge is removed from the charge trapping region.

Abstract: A method of erasing a flash memory device that improves reliability and reduces the decrease in erase speed. The state of erasure is determined either during an erase phase or a verify phase and the information is fedback to a controller that adjusts the erase vertical electrical field that is to be applied to the array. The vertical electrical field is adjusted by changing the gate voltage, the well voltage or changing both simultaneously.

Abstract: One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a substrate, the substrate having a core region and a periphery region; a charge trapping dielectric over the core region of the substrate; a gate dielectric in the periphery region of the substrate; buried bitlines under the charge trapping dielectric in the core region; and wordlines over the charge trapping dielectric in the core region, wherein the core region is substantially planar.

Abstract: A method of erasing a memory cell that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes simultaneously applying a first positive voltage across the gate and a second positive voltage to the first region, wherein the second positive voltage is greater than the first positive voltage.

Abstract: A memory device having multiple banks, each bank having multiple memory cells and a method of programming multiple memory cells in the device wherein a bias voltage is applied to a common source terminal of the multiple memory cells and a time varying voltage is applied to gates of the memory cells that are to be programmed. In one embodiment, the voltage applied to the gates of the memory cells to be programmed is a ramp voltage. In a second embodiment, the voltage applied to the gates of the memory cells to be programmed is an increasing step voltage. In another embodiment, the bias voltage applied to the common source terminal and the voltage applied to the control gates of the memory cells to be programmed are selected so that the current flowing through cells being programmed is reduced and that the leakage current from memory cells that are not to be programmed is substantially eliminated.

Abstract: A method of erasing a memory cell that includes a first region and a second region with a channel therebetween that has spillover electrons and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes generating neutralizing holes in the substrate, moving the neutralizing holes to the channel and substantially neutralizing the spillover electrons with the neutralizing holes moved to the channel.

Abstract: A method of erasing a memory cell that has a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains an initial amount of charge. The method includes applying a first cycle of voltages across the gate and the first region so that the first amount of charge is removed from the charge trapping region. A second amount of charge is written into the charge trapping region and subsequently a second cycle of one or more voltages is applied across the gate and the first region so that the second amount of charge is removed from the charge trapping region, wherein the initial applied voltage of the second cycle of voltages is equal to the final applied voltage of the first cycle of voltages.

Abstract: A method for erasing a flash EEPROM cell by applying a voltage differential between the control gate and the well of the memory cell. The voltage differential can be a ramped or stepped voltage applied to the control gate, a ramped or stepped voltage applied to the well, or a ramped or stepped voltage applied to the control gate and a ramped or stepped voltage applied to the well. The ramped voltages can have a constant slope or the slope can vary. The stepped voltages can be incremented equally or unequally. The voltages applied to the well or to the control gate is ramped or stepped until a selected number of memory cells verify as erased at which time the voltages applied to the well or to the control gate is clamped until the erase procedure is finished.

Abstract: A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of floating gate transistor memory cells, a plurality of wordlines connected to the cells and a power supply for generating erase pulses. A controller controls the power supply to apply an erase pulse to all wordlines which are not deselected. Then, an erase verify procedure is applied to the cells in sequence. If all cells connected to a wordline pass the erase verify test, the wordline is deselected such that subsequent erase pulses will not be applied to the wordline and possibly cause the cells to become overerased. In one embodiment of the invention, erase verify is performed on all of the cells after an erase pulse is applied. The erase operation is completed when all cells pass erase verify. In another embodiment, erase verify is applied to each cell in sequence, with erase pulses being applied until each current cell passes erase verify. The wordlines can be deselected individually or in groups.

Abstract: A flash Electrically-Erasable Programmable Read-Only Memory includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate. The state of erasure of the cells is determined by sensing the source voltage of the cells. An erase pulse is applied to the cells by a power supply which applies a source pull-up voltage to the cells configured in accordance with a predetermined function of the state of erasure. The power supply includes a variable current source and/or a resistor which are continuously adjusted as the erase operation progresses to provide an optimal vertical field across the tunnel oxide layers of the cells. Alternatively, the power supply can include a voltage regulator which is continuously adjusted to directly apply an optimal source voltage to the cells. The state of erasure can also be predetermined as a function of time or applied erase pulses, and the power supply adjusted in an open loop manner.

Abstract: A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate. The memory further includes a resistive power supply, a sensor, and a controller which cooperates with the power supply. The power supply applies a source voltage to the sources of the cells that can have a maximum value. An erase pulse is applied to the cells during which the power supply is configured to allow the source voltage to clamp to the maximum value. A monitoring pulse is then applied to the cells during which the power supply is configured to prevent the source voltage from clamping to the maximum value. The sensor senses the source voltage while the monitoring pulse is applied. As the source voltage is not clamped, it is substantially a function of band-to-band tunneling current and accurately indicates the average state of erasure of the cells.

Abstract: A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, and a power source for supplying a plurality of voltages to the cells. A controller controls the power source to apply at least one erase pulse to the cells. Then, at least one overerase correction or "soft programming" pulse is applied to the cells during which the source, drain and control gate voltages of the cells are such that the threshold voltages of overerased cells will be increased, but least erased cells will not be disturbed. The overerase correction pulses thereby tighten the threshold voltage distribution. A source to substrate bias voltage is applied for the duration of the overerase correction pulses which reduces the background leakage of the cells to a level at which the overerase correction operation can be effectively performed, even in applications with low supply voltages.

Abstract: A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a semiconductor substrate, and a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate formed on the substrate. A controller controls a power source to apply an operational pulse to the drain of a cell, and apply a source to substrate bias voltage to the cell while the operational pulse is being applied thereto, the bias voltage having a value selected to reduce or substantially eliminate leakage current in the cell. The operational pulse can be an overerase correction pulse. In this case, a voltage which is substantially equal to the bias voltage is applied to the control gate for the duration of the overerase correction pulse. The operational pulse can also be a programming pulse. In this case, a voltage which is higher than the bias voltage is applied to the control gate of the selected wordline for the duration of the programming pulse.