Patents by Inventor Ravishankar Arunachalam

Ravishankar Arunachalam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for short-circuit current modeling in CMOS integrated circuits
    Patent number: 7191113
    Abstract: A method and system for short-circuit current modeling in CMOS circuit provides improved accuracy for logic gate power dissipation models in computer-based verification and design tools. The model determines the short circuit current for each complementary pair within a CMOS circuit. Input and output voltage waveforms provided from results of a timing analysis are used to model the behavior one device of the complementary pair. The device is selected as the limiting device (the device transitioning to an “off state) from the direction of the logic transition being modeled, which is also the device that is not charging or discharging the output load. Therefore, the current through the selected device can be determined from the input and output waveforms and is equal to the short-circuit current prior to the saturation of the selected device.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: March 13, 2007
    Assignee: International Business Machines Corporation
    Inventors: Emrah Acar, Ravishankar Arunachalam, Sani Richard Nassif
  • Generation of refined switching windows in static timing analysis
    Patent number: 6988255
    Abstract: A method and structure to determine timing windows in a static timing analysis of an integrated circuit design, determines for at least one node in the integrated circuit design, an initial set of sub-windows and merges the sub-windows of the initial set into a final set of sub-windows.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: January 17, 2006
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Allen, Ravishankar Arunachalam, David J. Hathaway
  • Method and system for short-circuit current modeling in CMOS integrated circuits
    Publication number: 20040117169
    Abstract: A method and system for short-circuit current modeling in CMOS circuit provides improved accuracy for logic gate power dissipation models in computer-based verification and design tools. The model determines the short circuit current for each complementary pair within a CMOS circuit. Input and output voltage waveforms provided from results of a timing analysis are used to model the behavior one device of the complementary pair. The device is selected as the limiting device (the device transitioning to an “off state) from the direction of the logic transition being modeled, which is also the device that is not charging or discharging the output load. Therefore, the current through the selected device can be determined from the input and output waveforms and is equal to the short-circuit current prior to the saturation of the selected device.
    Type: Application
    Filed: December 17, 2002
    Publication date: June 17, 2004
    Applicant: International Business Machines Corporation
    Inventors: Emrah Acar, Ravishankar Arunachalam, Sani Richard Nassif
  • Generation of refined switching windows in static timing analysis
    Publication number: 20040060022
    Abstract: A method and structure to determine timing windows in a static timing analysis of an integrated circuit design, determines for at least one node in the integrated circuit design, an initial set of sub-windows and merges the sub-windows of the initial set into a final set of sub-windows.
    Type: Application
    Filed: September 18, 2003
    Publication date: March 25, 2004
    Inventors: Robert J. Allen, Ravishankar Arunachalam, David J. Hathaway
  • Generation of refined switching windows in static timing analysis
    Patent number: 6651229
    Abstract: A method and structure to determine timing windows in a static timing analysis of an integrated circuit design, determines for at least one node in the integrated circuit design, an initial set of sub-windows and merges the sub-windows of the initial set into a final set of sub-windows.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: November 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Allen, Ravishankar Arunachalam, David J. Hathaway
  • Generation of refined switching windows in static timing analysis
    Publication number: 20030070150
    Abstract: A method and structure to determine timing windows in a static timing analysis of an integrated circuit design, determines for at least one node in the integrated circuit design, an initial set of sub-windows and merges the sub-windows of the initial set into a final set of sub-windows.
    Type: Application
    Filed: October 9, 2001
    Publication date: April 10, 2003
    Inventors: Robert J. Allen, Ravishankar Arunachalam, David J. Hathaway