Abstract: An integrated circuit having power supply circuitry configured to generate a temperature dependent power supply voltage is provided. The power supply circuitry may include temperature sensors formed at different regions on the integrated circuit. The power supply circuitry may use a selected one of the temperature sensors to vary the temperature dependent power supply voltage. The power supply circuitry may include voltage clamping circuitry configured to clip the power supply voltage to an upper fixed voltage level when the power supply voltage exceeds a first predetermined threshold and to clip the power supply voltage to a lower fixed voltage level when the power supply voltage falls below a second predetermined threshold. The power supply circuitry may also include voltage overshoot-undershoot protection circuitry configured to keep the temperature dependent power supply voltage within a specified voltage range in the presence of transient perturbations in the temperature dependent power supply voltage.

Abstract: A level conversion architecture that accommodates signals traveling between logic blocks operating at corresponding voltage levels is provided. The architecture includes pass gates connected in series between the logic blocks. One of the gates of the pass gates is supplied with a selectable gate voltage supply. The selectable gate voltage supply is selected from a plurality of voltages based on a configuration random access memory (CRAM) setting. In one embodiment, a half latch is connected to one of the pass gates. In this embodiment, the half latch is part of a feedback loop to minimize power leakage of a logic element in one of the logic blocks. A method for managing power consumption and providing voltage level conversion between regions of an integrated circuit is also provided.

Abstract: A level conversion architecture that accommodates signals traveling between logic blocks operating at corresponding voltage levels is provided. The architecture includes pass gates connected in series between the logic blocks. One of the gates of the pass gates is supplied with a selectable gate voltage supply. The selectable gate voltage supply is selected from a plurality of voltages based on a configuration random access memory (CRAM) setting. In one embodiment, a half latch is connected to one of the pass gates. In this embodiment, the half latch is part of a feedback loop to minimize power leakage of a logic element in one of the logic blocks. A method for managing power consumption and providing voltage level conversion between regions of an integrated circuit is also provided.

Abstract: An interconnect circuit includes a driver circuit and a receiver circuit. The receiver circuit couples to the driver circuit. The driver circuit is configured to receive an input signal and to derive from the input signal a limited swing driver output signal. The receiver circuit is configured to derive from the limited swing driver output signal a limited swing receiver output signal.