Patents by Inventor Ravi Venkatesan

Ravi Venkatesan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11151074
    Abstract: Methods and apparatus to implement multiple inference compute engines are disclosed herein. A disclosed example apparatus includes a first inference compute engine, a second inference compute engine, and an accelerator on coherent fabric to couple the first inference compute engine and the second inference compute engine to a converged coherency fabric of a system-on-chip, the accelerator on coherent fabric to arbitrate requests from the first inference compute engine and the second inference compute engine to utilize a single in-die interconnect port.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: October 19, 2021
    Assignee: Intel Corporation
    Inventors: Israel Diamand, Roni Rosner, Ravi Venkatesan, Shlomi Shua, Oz Shitrit, Henrietta Bezbroz, Alexander Gendler, Ohad Falik, Zigi Walter, Michael Behar, Shlomi Alkalay
  • Publication number: 20190370209
    Abstract: Methods and apparatus to implement multiple inference compute engines are disclosed herein. A disclosed example apparatus includes a first inference compute engine, a second inference compute engine, and an accelerator on coherent fabric to couple the first inference compute engine and the second inference compute engine to a converged coherency fabric of a system-on-chip, the accelerator on coherent fabric to arbitrate requests from the first inference compute engine and the second inference compute engine to utilize a single in-die interconnect port.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 5, 2019
    Inventors: Israel Diamand, Roni Rosner, Ravi Venkatesan, Shlomi Shua, Oz Shitrit, Henrietta Bezbroz, Alexander Gendler, Ohad Falik, Zigi Walter, Michael Behar, Shlomi Alkalay
  • Publication number: 20180285916
    Abstract: A system including: at least one processor; and at least one memory having stored thereon computer program code that, when executed by the at least one processor, instructs the at least one processor to: retrieve, from an account host, an account credit amount associated with a user account; convert the credit amount to a monetary value based on one or more conversion rules associated with the account host; and provide an available balance of a virtual rewards account to correspond to the monetary value.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 4, 2018
    Inventors: Andrew Althauser, Ravi Venkatesan, Larry Wine, Craig McLaughlin, Jason Phillips, Jerry Bulger
  • Publication number: 20140278700
    Abstract: A system that receives plurality of data that includes dimensions (e.g., revenue, profit margin, level of effort, urgency or alignment to the organization's technology strategy) and criteria (e.g., business unit, product, or service) that are relevant to drive an organization's priorities. The system generates a visual display on which a representation (e.g., a sphere, circle, square, or other shape) for each of the projects is depicted. In various embodiments, the user may select one dimension to be used as an x-axis scale of the visual display and a second dimension to be used as a y-axis scale of the visual display. The system plots a representation for each project against various dimensions that are meaningful to the business organization.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 18, 2014
    Applicant: Cbeyond
    Inventors: DAVID R. GRANTIER, CHRISTOPHER J. WATKINS, ANDREW BRYANT, REED C. SELLERS, RAVI VENKATESAN, DENISE ROGERS, RHONDA CAPONE, CARRIE ANN WHEELER
  • Publication number: 20060181953
    Abstract: A memory system includes storage cells, a respective one of which is configured to store a fixed charge therein when a write voltage applied thereto is above a predetermined threshold voltage and to discharge the fixed charge therefrom when the write voltage applied thereto is below the threshold voltage. The storage cells may be charged and/or discharged at a latency that is a function of a voltage differential between the write voltage and the threshold voltage. A variable-latency write circuit for the storage cells is configured to dynamically vary the voltage differential between the write voltage and the threshold voltage to provide a variable-latency write operation that stores the fixed charge therein or discharges the fixed charge therefrom. Related methods are also discussed.
    Type: Application
    Filed: February 11, 2005
    Publication date: August 17, 2006
    Inventors: Eric Rotenberg, Ravi Venkatesan, Ahmed Al-Zawawi