Abstract: A method and apparatus for controlling the admission of data packets into a network element is described. In an embodiment, a method for controlling admittance of a data packet into a memory buffer includes performing, prior to queuing the data packet for routing by a processor, the following: (1) receiving a data packet from one of at least two different ports, (2) determining a priority value within the data packet, and (3) determining an admittance group identifier for the data packet based on the priority value and the port the data packet was received. The method also comprises queuing the data packet from the memory buffer to one of a number of queues for routing by the processor upon determining that a number of data packets stored in the memory buffer and having the admittance group identifier is not greater than a threshold value.

Abstract: A computer system includes a processor having a cache memory and coupled to a system controller through a processor bus, a main memory coupled to the system controller through a dedicated memory bus, and a local bus master coupled to the system controller through a local bus. The system controller includes a write register and a read register that form a first path for coupling bus signals between the processor bus and main memory, and the system controller also includes a second read register that with the write buffer forms a second path to the main memory for coupling bus signals between the local bus and main memory. The first and second paths of the system controller decouple the processor and local buses, allowing processor-cache operations to proceed concurrently with operations between the local bus master and main memory.