Abstract: In an interconnect apparatus for interconnecting at least one host to at least a plurality of presentation registers provide a presentation interface for the device to the host. The interconnect apparatus includes memory for holding the presentation registers and a governor operable to manage the presentation registers in the memory.

Abstract: An instruction pipeline is provided which can handle stack cache misses without stalling. The instruction pipeline includes a stack cache fetch stage configured to retrieve data from a stack cache and a data cache fetch stage configured to retrieve data from a data cache. The instruction pipeline writes data out during a write stage that occurs at the end of the instruction pipeline. Thus, instead of stalling on a stack cache miss, the instruction pipeline can continue processing and issuing a data cache request in the data cache fetch stage for the required data. In addition, some embodiments of the invention include a feedback path between the stack cache fetch stage and pipeline stages following the stack cache fetch stage. If the stack cache fetch stage requires data from an address that is also being used by a later pipeline stage, the data in the later pipeline stage is sent to the stack cache fetch stage through the feedback path.

Abstract: An execution unit for a stack based computing system that can combine instructions into instruction groups for concurrent execution is provided. In accordance with one embodiment, the instructions of the stack based computing system are separated into different instruction types. Certain combinations of instruction types can be combined into instruction groups for concurrent execution. The execution unit includes an instruction folding unit that is configured to determine the instruction type of instructions and combine the instructions into instruction groups, and an instruction pipeline that is configured to process both instructions and instruction groups. In one embodiment, the instruction folding unit includes: an instruction type estimator which estimates the instruction types of various instructions; an instruction selector, which selects the instruction types from the estimated instruction types; and a folding logic circuit which combines the instructions into instruction groups.

Abstract: A length decoder that rapidly calculates the group lengths of groups of variable length data words is provided. In accordance with one embodiment, a length decoder includes a length estimator and a length selector. The length estimator, estimates a length for each data word assuming the data word is the first member of a group. The length selector then selects the proper estimate based upon the actual length of the data word. Specifically, one embodiment of the length decoder can be used to calculate the length of instruction groups in a stack based computing system.

Abstract: An execution unit that executes multiple instructions as a single instruction group during a single processing cycle is provided. The execution unit handles problem causing instruction groups by trapping the problem causing instruction group using the trap logic of a processing unit. The reissue logic circuits restores the program state of the execution unit prior to issuance of the trapped instruction group. The reissue logic circuit then forces each instruction of the instruction group to be issued as a separate instruction. Specifically, the reissue logic inhibits folding of instructions into instruction groups by an instruction-folding unit. After the instructions of the trapped instruction group are executed, the reissue logic re-enables folding by the instruction-folding unit.