Abstract: A method and apparatus for prefetching superblocks in a computer processing system having a fetch mechanism for fetching instructions for execution includes the step of controlling the fetch mechanism to begin fetching at a starting address of a current superblock. A superblock includes a set of instructions in consecutive address locations terminated by a branch instruction known to have been taken. A Superblock Target Buffer (STB) is supplied with the starting address of the current superblock. The STB has a plurality of entries each indexed by a starting address of a superblock and including a run length of the superblock and a target address of the terminating branch of the superblock. The run length corresponds to the sum of a length of the terminating branch and the difference between a starting address of the terminating branch of the superblock and the starting address of the superblock.

Abstract: A method for associating subroutine calls with corresponding targets includes the step of maintaining a first table of entries. Each entry in the first table includes: a first table first address identifying an entry point address for a corresponding subroutine; and a first table second address identifying a return address of a return for the corresponding subroutine. A second table of entries is also maintained. Each entry in the second table includes: a second table first address identifying a return address of a return for a respective subroutine called by a corresponding subroutine call instruction; a second table second address identifying a target address of the return for the respective subroutine; and a second table third address identifying an entry point address for the respective subroutine. It is determined whether the second table stores an entry whose second table first address corresponds to a return address of a return for a considered subroutine.

Abstract: A computer processing apparatus includes a buffer called a decoded instruction buffer (DIB), which is used to store groups of commands representing instructions that can be executed in parallel. Each pattern in a DIB group may be an encoding of a long instruction termed a long decoded instruction (LDI). The DIB works in conjunction with a conventional computer processing apparatus consisting of a memory system, an instruction queue, and an instruction dispatch unit feeding into a set of execution units. When an instruction is not available in the DIB, this and subsequent instructions are fetched from the memory system into the instruction queue and executed in a conventional way.Simultaneous with the execution of instructions by the conventional apparatus, a group formatter creates a set of LDIs, each of which is an alternate encoding of a set of the original instructions which can be executed in parallel.

Abstract: A method of generating the layout of CMOS cells from a high-level functional description of the cells, as well as generating the particular details of the CMOS device. In particular, the image of the chip is formed having the polysilicon gates of the transistors on the n-side vertically aligned with those of the p-side vertically aligned with those of the p-side to minimize the wiring effort. The interconnections between the source and drains are orthogonal to the gates, and run along one layer of metal.

Abstract: Method and apparatus for the physical design of very large scale integrated (VLSI) circuits, and in particular the interconnection and wire routing between circuits formed on a chip. Apparatus is set forth for determining the wire routings in a VLSI circuit comprised of cells, wherein the cells are composed of electronic devices functioning as logic gates. Groups of cells may be interconnected to function as flip flops, shift registers and the like. A supervisory controller communicates with n, where n is an integer, identical multi-port processors, with one processor dedicated to each cell, for determining the wire routings between the respective cells. Each processor communicates simultaneously with its four adjacent neighbor processors to determine channel routings from one point to the next in the array of cells, wherein a channel routing includes vertical and horizontal paths. Following determination of global channel routings, exact vertical and horizontal tracks for the wire paths are assigned.

Abstract: Method and apparatus for the physical design of very large scale integrated (VLSI) circuits, and in particular the interconnection and wire routing between circuits formed on a chip. Apparatus is set forth for determining the wire routings in a VLSI circuit comprised of cells, wherein the cells are composed of electronic devices functioning as logic gates. Groups of cells may be interconnected to function as flip flops, shift registers and the like. A supervisory controller communicates with n, where n is an integer, identical multi-port processors, with one processor dedicated to each cell, for determining the wire routings between the respective cells. Each processor communicates simultaneously with its four adjacent neighbor processors to determine channel routings from one point to the next in the array of cells, wherein a channel routing includes vertical and horizontal paths. Following determination of global channel routings, exact vertical and horizontal tracks for the wire paths are assigned.