Patents by Inventor Ravindranath D. Shrivastava
Ravindranath D. Shrivastava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240097656Abstract: Methods and devices to reduce glitches in phase shifters implementing high isolation switches are disclosed. Such glitches occur at the output of the phase shifters when transitioning from one phase shift to another. The disclosed method implements delays in various steps of the phase shifter transitions. Exemplary embodiments implementing single-pole multi-throw are provided and exemplary performance of the disclosed methods are also presented. The described methods are also applicable to multi-step attenuators.Type: ApplicationFiled: September 19, 2022Publication date: March 21, 2024Inventors: Ravindranath D. SHRIVASTAVA, Fleming LAM, Payman SHANJANI
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Publication number: 20240063789Abstract: A FET switch stack and a method to operate a FET switch stack. The FET switch stack includes a stacked arrangement of body bypass FET switches connected across respective common body resistors. The body bypass FET switches bypass the respective common body resistors during the OFF steady state of the FET switch stack and do not bypass the respective common body resistors during the ON steady state.Type: ApplicationFiled: September 25, 2023Publication date: February 22, 2024Inventors: Eric S. SHAPIRO, Ravindranath D. SHRIVASTAVA, Fleming LAM, Matt ALLISON
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Publication number: 20240030906Abstract: Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.Type: ApplicationFiled: August 21, 2023Publication date: January 25, 2024Inventors: Ravindranath D. SHRIVASTAVA, Simon WILLARD, Peter BACON
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Patent number: 11835978Abstract: Methods and devices to reduce or remove slumps in power supplies are disclosed. The disclosed teachings can serve various applications, such as applications implementing RF switches. Using such teachings, an integrated method can benefit from two different modes of operation where either an external or an internal charge pump can be used to provide a desired negative voltage to various components within the integrated circuit. This can be done by disposing a larger load capacitor outside the integrated circuit and without compromising any die space requirement.Type: GrantFiled: August 23, 2022Date of Patent: December 5, 2023Assignee: pSemi CorporationInventors: Ravindranath D. Shrivastava, Payman Shanjani
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Patent number: 11777485Abstract: Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.Type: GrantFiled: April 26, 2022Date of Patent: October 3, 2023Assignee: PSEMI CORPORATIONInventors: Ravindranath D. Shrivastava, Simon Willard, Peter Bacon
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Publication number: 20230291360Abstract: Circuits and methods for improving the noise figure (NF) of an amplifier, particularly an LNA, in high-gain modes while improving the IIP3 of the amplifier in low-gain modes. The source of an amplifier common-source FET is coupled to circuit ground thorough a degeneration circuit comprising a two-port inductor and a bypass switch coupled in parallel with the inductor. A switched feedback circuit is coupled between the gate of the common-source FET and a feedback node in the amplifier output signal path. During a low gain mode, the inductor is entirely bypassed and the enabled feedback circuit lowers the input impedance of the common-source FET and reduces the gain of the amplifier circuit, essentially eliminating the need for a degeneration inductor. During a high gain mode, the source of the common-source FET is coupled to circuit ground through the inductor and the feedback circuit is disabled. Other gain modes are supported.Type: ApplicationFiled: March 16, 2023Publication date: September 14, 2023Inventors: Rong Jiang, Khushali Shah, Ravindranath D. Shrivastava, Parvez H. Daruwalla
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Publication number: 20230283277Abstract: A FET switch stack has a stacked arrangement of FET switches, a gate resistor network with ladder resistors and common gate resistors, and a gate resistor bypass arrangement. The bypass arrangement has a first set of bypass switches connected across the gate resistors and a second set of bypass switches connected across the ladder resistors. Bypass occurs during at least a portion of the transition state of the stacked arrangement of FET switches.Type: ApplicationFiled: March 14, 2023Publication date: September 7, 2023Inventors: Ravindranath D. SHRIVASTAVA, Alper GENC
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Patent number: 11722162Abstract: Fail-safe methods and devices to protect the receiver of a transceiver in the event of an antenna failure are disclosed. The described devices implement inductive and capacitive elements to replace switches and can be used in any communication system or electronic circuit where the protection of a portion of the device from higher power signals is required. The inductive elements can be implemented using already existing inductors that are constituents of the receiver matching network. Configurations with off-chip capacitive or inductive components are also possible.Type: GrantFiled: February 2, 2022Date of Patent: August 8, 2023Assignee: PSEMI CORPORATIONInventors: Chengkai Luo, Payman Shanjani, Ravindranath D. Shrivastava
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Publication number: 20230246659Abstract: Fail-safe methods and devices to protect the receiver of a transceiver in the event of an antenna failure are disclosed. The described devices implement inductive and capacitive elements to replace switches and can be used in any communication system or electronic circuit where the protection of a portion of the device from higher power signals is required. The inductive elements can be implemented using already existing inductors that are constituents of the receiver matching network. Configurations with off-chip capacitive or inductive components are also possible.Type: ApplicationFiled: February 2, 2022Publication date: August 3, 2023Inventors: Chengkai LUO, Payman SHANJANI, Ravindranath D. SHRIVASTAVA
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Patent number: 11671135Abstract: An apparatus for reducing switching time of RF FET switching devices is described. A FET switch stack includes a stacked arrangement of FET switches and a plurality of gate feed arrangements, each coupled at a different height of the stacked arrangement. A circuital arrangement with a combination of a series RF FET switch and a shunt RF FET switch, each having a stack of FET switches, is also described. The shunt switch has one or more shunt gate feed arrangements with a number of bypass switches that is less than the number of FET switches in the shunt stack.Type: GrantFiled: October 1, 2021Date of Patent: June 6, 2023Assignee: PSEMI CORPORATIONInventors: Ravindranath D. Shrivastava, Fleming Lam, Payman Shanjani
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Patent number: 11632107Abstract: A FET switch stack has a stacked arrangement of FET switches, a gate resistor network with ladder resistors and common gate resistors, and a gate resistor bypass arrangement. The bypass arrangement has a first set of bypass switches connected across the gate resistors and a second set of bypass switches connected across the ladder resistors. Bypass occurs during at least a portion of the transition state of the stacked arrangement of FET switches.Type: GrantFiled: October 1, 2021Date of Patent: April 18, 2023Assignee: PSEMI CORPORATIONInventors: Ravindranath D. Shrivastava, Alper Genc
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Publication number: 20230105033Abstract: An apparatus for reducing switching time of RF FET switching devices is described. A FET switch stack includes a stacked arrangement of FET switches and a plurality of gate feed arrangements, each coupled at a different height of the stacked arrangement. A circuital arrangement with a combination of a series RF FET switch and a shunt RF FET switch, each having a stack of FET switches, is also described. The shunt switch has one or more shunt gate feed arrangements with a number of bypass switches that is less than the number of FET switches in the shunt stack.Type: ApplicationFiled: October 1, 2021Publication date: April 6, 2023Inventors: Ravindranath D. SHRIVASTAVA, Fleming LAM, Payman SHANJANI
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Publication number: 20230107974Abstract: A FET switch stack has a stacked arrangement of FET switches, a gate resistor network with ladder resistors and common gate resistors, and a gate resistor bypass arrangement. The bypass arrangement has a first set of bypass switches connected across the gate resistors and a second set of bypass switches connected across the ladder resistors. Bypass occurs during at least a portion of the transition state of the stacked arrangement of FET switches.Type: ApplicationFiled: October 1, 2021Publication date: April 6, 2023Inventors: Ravindranath D. SHRIVASTAVA, Alper GENC
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Patent number: 11616475Abstract: Circuits and methods for improving the noise figure (NF) of an amplifier, particularly an LNA, in high-gain modes while improving the IIP3 of the amplifier in low-gain modes. The source of an amplifier common-source FET is coupled to circuit ground thorough a degeneration circuit comprising a two-port inductor and a bypass switch coupled in parallel with the inductor. A switched feedback circuit is coupled between the gate of the common-source FET and a feedback node in the amplifier output signal path. During a low gain mode, the inductor is entirely bypassed and the enabled feedback circuit lowers the input impedance of the common-source FET and reduces the gain of the amplifier circuit, essentially eliminating the need for a degeneration inductor. During a high gain mode, the source of the common-source FET is coupled to circuit ground through the inductor and the feedback circuit is disabled. Other gain modes are supported.Type: GrantFiled: January 5, 2021Date of Patent: March 28, 2023Assignee: pSemi CorporationInventors: Rong Jiang, Khushali Shah, Ravindranath D. Shrivastava, Parvez Daruwalla
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Publication number: 20220321113Abstract: Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.Type: ApplicationFiled: April 26, 2022Publication date: October 6, 2022Inventors: Ravindranath D. SHRIVASTAVA, Simon WILLARD, Peter BACON
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Patent number: 11405031Abstract: A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.Type: GrantFiled: August 16, 2021Date of Patent: August 2, 2022Assignee: PSEMI CORPORATIONInventors: Ravindranath D. Shrivastava, Fleming Lam, Payman Shanjani
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Patent number: 11405034Abstract: A FET switch stack and a method to operate a FET switch stack. The FET switch stack includes a stacked arrangement of body bypass FET switches connected across respective common body resistors. The body bypass FET switches bypass the respective common body resistors during the OFF steady state of the FET switch stack and do not bypass the respective common body resistors during the ON steady state.Type: GrantFiled: May 14, 2021Date of Patent: August 2, 2022Assignee: PSEMI CORPORATIONInventors: Eric S. Shapiro, Ravindranath D. Shrivastava, Fleming Lam, Matt Allison
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Publication number: 20220216833Abstract: Circuits and methods for improving the noise figure (NF) of an amplifier, particularly an LNA, in high-gain modes while improving the IIP3 of the amplifier in low-gain modes. The source of an amplifier common-source FET is coupled to circuit ground thorough a degeneration circuit comprising a two-port inductor and a bypass switch coupled in parallel with the inductor. A switched feedback circuit is coupled between the gate of the common-source FET and a feedback node in the amplifier output signal path. During a low gain mode, the inductor is entirely bypassed and the enabled feedback circuit lowers the input impedance of the common-source FET and reduces the gain of the amplifier circuit, essentially eliminating the need for a degeneration inductor. During a high gain mode, the source of the common-source FET is coupled to circuit ground through the inductor and the feedback circuit is disabled. Other gain modes are supported.Type: ApplicationFiled: January 5, 2021Publication date: July 7, 2022Inventors: Rong Jiang, Khushali Shah, Ravindranath D. Shrivastava, Parvez Daruwalla
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Patent number: 11329642Abstract: Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.Type: GrantFiled: March 15, 2021Date of Patent: May 10, 2022Assignee: PSEMI CORPORATIONInventors: Ravindranath D. Shrivastava, Simon Willard, Peter Bacon
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Patent number: 10291208Abstract: A method and apparatus for adjusting the slope of insertion loss of digital step attenuator (DSA). The DSA is implemented on an integrated circuit. The DSA has two series inductances that are introduced between the input of DSA cell and a resistor in the cell, and the output of DSA cell and another resistor in the cell. In one embodiment, adjustment in the value of the series inductances is as achieved by altering the locations of the input port and the output ports. In another embodiment, adjustment in the value of the inductances is achieved by tailoring the length and width of the conductor trace used to connect the input and output ports to the series resistors. The adjustment in the values of the inductances provides a means by which the roll-off of the insertion loss as a function of frequency in the attenuation state can be controlled.Type: GrantFiled: July 9, 2018Date of Patent: May 14, 2019Assignee: pSemi CorporationInventors: Ravindranath D. Shrivastava, Raul Inocencio Alidio