Patents by Inventor Ravindranath Kollipara
Ravindranath Kollipara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9798628Abstract: Memory system enabling memory mirroring in single write operations. The memory system includes a memory channel which can store duplicate copies of a data element into multiple locations in the memory channel. The multiple locations are disposed in different memory modules and have different propagation times with respect to a data signal transmitted from the memory controller. In a write operation, the relative timings of the chip select, command and address signals among the multiple locations are adjusted according to the data propagation delay. As a result, a data element can be written into the multiple locations responsive to a data signal transmitted from the memory controller in a single transmission event.Type: GrantFiled: December 12, 2014Date of Patent: October 24, 2017Assignee: Rambus Inc.Inventors: Steven Woo, David Secker, Ravindranath Kollipara
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Patent number: 9747230Abstract: A memory system includes a two memory modules and a memory controller. The memory modules each include at least a first memory package corresponding to a first number of memory ranks (e.g. one memory rank) and a second memory package corresponding to a second number of memory ranks (e.g. two memory ranks) that is greater than the first number of memory ranks. For each module, the memory packages may be asymmetrically staggered such that one memory package is further from the memory controller than the other memory package. The memory controller is coupled to the memory packages of both modules via a common data line and generates control information for controlling the on-die termination (ODT) of the memory packages.Type: GrantFiled: October 14, 2013Date of Patent: August 29, 2017Assignee: Rambus Inc.Inventors: Minghui Han, Amir Amirkhany, Ravindranath Kollipara, Ralf Michael Schmitt
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Publication number: 20170024348Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.Type: ApplicationFiled: October 10, 2016Publication date: January 26, 2017Inventors: AMIR AMIRKHANY, SURESH RAJAN, RAVINDRANATH KOLLIPARA, IAN SHAEFFER, DAVID A. SECKER
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Patent number: 9489323Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.Type: GrantFiled: February 18, 2014Date of Patent: November 8, 2016Assignee: Rambus Inc.Inventors: Amir Amirkhany, Suresh Rajan, Ravindranath Kollipara, Ian Shaeffer, David A. Secker
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Publication number: 20160291894Abstract: System and method for dynamic termination control to enable use of an increased number of memory modules on a single channel. In some embodiments, six or eight DIMMs are coupled to a single channel. The dynamic termination scheme can include configurations for input bus termination (IBT) on each of the memory modules for the address bus/command bus and configurations for on-die termination (ODT) one each of the memory modules for the data bus.Type: ApplicationFiled: February 23, 2016Publication date: October 6, 2016Inventors: Chi-Ming YEUNG, David SECKER, Ravindranath KOLLIPARA, Shajith Musaliar SIRAJUDEEN, Yoshie NAKABAYASHI
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Patent number: 9373384Abstract: An embodiment is directed to an integrated circuit device having programmable input capacitance. For example, a programmable register of a memory device may store a value representative of an adjustment to the input capacitance value of a control pin. An embodiment is directed to controlling the skew of a synchronous memory system by allowing programmability of the lighter loaded pins in order to increase their load to match the more heavily loaded pins. By matching lighter loaded pins to more heavily loaded pins, the system exhibits improved synchronization of propagation delays of the control and address pins. In addition, an embodiment provides the ability to vary the loading depending on how many ranks are on the device.Type: GrantFiled: March 18, 2013Date of Patent: June 21, 2016Assignee: Rambus Inc.Inventors: Ravindranath Kollipara, Lei Luo, Ian Shaeffer
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Patent number: 9336834Abstract: The disclosed embodiments relate to the design of a memory system which includes a set of one or more memory modules, wherein each memory module in the set has a clamshell configuration, wherein pairs of opposing memory packages containing memory chips are located on opposite sides of the memory module. The memory system also includes a multi-drop path containing signal lines which pass through the set of memory modules, and are coupled to memory packages in the set of memory modules. For a given signal line in the multi-drop path, a first memory package and a second memory package that comprise a given pair of opposing memory packages are coupled to the given signal line at a first location and a second location, respectively, wherein the first location and the second location are separated from each other by a distance d1 along the given signal line.Type: GrantFiled: February 7, 2012Date of Patent: May 10, 2016Assignee: Rambus Inc.Inventors: Ian Shaeffer, Ravindranath Kollipara
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Patent number: 9298228Abstract: A computing system having a memory riser sub-system. The computing system includes a motherboard with a memory module connector and a riser card inserted into the first memory module connector. A first mezzanine card is connected to the riser card. The first mezzanine card includes a first mezzanine memory module connector for a first memory module and a second mezzanine memory module connector for a second memory module. A memory channel electrically connects the memory controller to the first mezzanine memory module connector and the second mezzanine module connector via the motherboard, the first riser card and the first mezzanine card. The memory channel may be divided into a first data sub-channel connected to the first mezzanine memory module connector and a second data sub-channel connected to the second mezzanine memory module connector.Type: GrantFiled: July 27, 2015Date of Patent: March 29, 2016Assignee: Rambus Inc.Inventors: Abhijit M. Abhyankar, Ravindranath Kollipara, Thomas J. Giovannini, Ming Li, David A. Secker, Arun Vaidyanath, Donald R. Mullen, Adrian F. Torres
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Patent number: 9281816Abstract: Alternating on-die termination impedances are applied within an integrated circuit device to up-convert signal reflections to higher frequencies that are attenuated by the signaling channel as the reflections propagate toward an intended signal receiver. Through this approach, the disruptive effect of reflected signals may be significantly reduced with relatively little overhead within the interconnected integrated circuit devices and little or no change to the printed circuit board or other interconnect medium. Changes to the printed circuit board or other interconnect medium can be made to further increase attenuation over the frequency band of the up-converted reflection and outside of the transmission band of signals of interest.Type: GrantFiled: December 22, 2012Date of Patent: March 8, 2016Assignee: Rambus Inc.Inventors: Amir Amirkhany, Farshid Aryanfar, Ravindranath Kollipara, Xingchao (Chuck) Yuan
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Publication number: 20150331817Abstract: A memory system includes a two memory modules and a memory controller. The memory modules each include at least a first memory package corresponding to a first number of memory ranks (e.g. one memory rank) and a second memory package corresponding to a second number of memory ranks (e.g. two memory ranks) that is greater than the first number of memory ranks For each module, the memory packages may be asymmetrically staggered such that one memory package is further from the memory controller than the other memory package. The memory controller is coupled to the memory packages of both modules via a common data line and generates control information for controlling the on-die termination (ODT) of the memory packages.Type: ApplicationFiled: October 14, 2013Publication date: November 19, 2015Inventors: Minghui HAN, Amir AMIRKHANY, Ravindranath KOLLIPARA, Ralf Michael SCHMITT
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Publication number: 20150309899Abstract: Memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.Type: ApplicationFiled: December 12, 2014Publication date: October 29, 2015Inventors: Steven WOO, David SECKER, Ravindranath KOLLIPARA
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Publication number: 20150309529Abstract: Memory system enabling memory mirroring in single write operations. The memory system includes a memory channel which can store duplicate copies of a data element into multiple locations in the memory channel. The multiple locations are disposed in different memory modules and have different propagation times with respect to a data signal transmitted from the memory controller. In a write operation, the relative timings of the chip select, command and address signals among the multiple locations are adjusted according to the data propagation delay. As a result, a data element can be written into the multiple locations responsive to a data signal transmitted from the memory controller in a single transmission event.Type: ApplicationFiled: December 12, 2014Publication date: October 29, 2015Inventors: Steven WOO, David SECKER, Ravindranath KOLLIPARA
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Publication number: 20140347092Abstract: Alternating on-die termination impedances are applied within an integrated circuit device to up-convert signal reflections to higher frequencies that are attenuated by the signaling channel as the reflections propagate toward an intended signal receiver. Through this approach, the disruptive effect of reflected signals may be significantly reduced with relatively little overhead within the interconnected integrated circuit devices and little or no change to the printed circuit board or other interconnect medium. Changes to the printed circuit board or other interconnect medium can be made to further increase attenuation over the frequency band of the up-converted reflection and outside of the transmission band of signals of interest.Type: ApplicationFiled: December 22, 2012Publication date: November 27, 2014Inventors: Amir Amirkhany, Farshid Aryanfar, Ravindranath Kollipara, Xingchao (Chuck) Yuan
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Publication number: 20140237152Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.Type: ApplicationFiled: February 18, 2014Publication date: August 21, 2014Applicant: Rambus Inc.Inventors: AMIR AMIRKHANY, SURESH RAJAN, RAVINDRANATH KOLLIPARA, IAN SHAEFFER, DAVID A. SECKER
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Publication number: 20130314968Abstract: The disclosed embodiments relate to the design of a memory system which includes a set of one or more memory modules, wherein each memory module in the set has a clamshell configuration, wherein pairs of opposing memory packages containing memory chips are located on opposite sides of the memory module. The memory system also includes a multi-drop path containing signal lines which pass through the set of memory modules, and are coupled to memory packages in the set of memory modules. For a given signal line in the multi-drop path, a first memory package and a second memory package that comprise a given pair of opposing memory packages are coupled to the given signal line at a first location and a second location, respectively, wherein the first location and the second location are separated from each other by a distance d1 along the given signal line.Type: ApplicationFiled: February 7, 2012Publication date: November 28, 2013Inventors: Ian Shaeffer, Ravindranath Kollipara
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Patent number: 8588012Abstract: Termination of a high-speed signaling link is effected by simultaneously engaging on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link.Type: GrantFiled: June 1, 2011Date of Patent: November 19, 2013Assignee: Rambus, Inc.Inventors: John Wilson, Joong-Ho Kim, Ravindranath Kollipara, David Secker, Kyung Suk Oh
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Publication number: 20130258755Abstract: An embodiment is directed to an integrated circuit device having programmable input capacitance. For example, a programmable register of a memory device may store a value representative of an adjustment to the input capacitance value of a control pin. An embodiment is directed to controlling the skew of a synchronous memory system by allowing programmability of the lighter loaded pins in order to increase their load to match the more heavily loaded pins. By matching lighter loaded pins to more heavily loaded pins, the system exhibits improved synchronization of propagation delays of the control and address pins. In addition, an embodiment provides the ability to vary the loading depending on how many ranks are on the device.Type: ApplicationFiled: March 18, 2013Publication date: October 3, 2013Applicant: RAMBUS, INC.Inventors: Ravindranath Kollipara, Lei Luo, Ian Shaeffer
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Publication number: 20110314200Abstract: Termination of a high-speed signaling link is effected by simultaneously engaging on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link.Type: ApplicationFiled: June 1, 2011Publication date: December 22, 2011Inventors: John Wilson, Joong-Ho Kim, Ravindranath Kollipara, David Secker, Kyung Suk Oh
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Publication number: 20110119425Abstract: The disclosure relates to a detachable signalling interconnect apparatus that provides connectivity between two or more components of a memory system in conjunction with different modes of operation of the components. The memory system comprises: a first socket to receive a first memory module; a second socket to receive a second memory module; a detachable signal-interconnect; and a memory controller coupled to the detachable signal-interconnect and configured to define a first mode of operation and a second mode of operation, wherein in the first mode of operation the detachable signal-interconnect is to couple the memory-controller to the first memory module and in the second mode of operation the detachable signal-interconnect is to couple the memory controller to the first memory module and the second memory module.Type: ApplicationFiled: June 30, 2008Publication date: May 19, 2011Applicant: RAMBUS INC.Inventors: Ravindranath Kollipara, Xingchao Yuan, Frank Lambrecht, Ming Li, Richard E. Perego, Qi Lin, David Nguyen, Kyung Suk Oh
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Publication number: 20110033007Abstract: A system comprising: a first integrated circuit device having a multi-band transmission circuit; second and third integrated circuit devices having respective multi-band reception circuits; and a signaling link including a first stub coupled to the multi-band transmission circuit to receive a multi-band signal therefrom, second and third stubs coupled to the multi-band reception circuits of the second and third integrated circuit devices, respectively, to deliver the multi-band signal thereto, and a plurality of channel segments that extend between the first, second and third stubs to convey the multi-band transmission signal therebetween, and wherein at least one of a physical length, impedance or propagation constant of at least one of the first stub, second stub, third stub or channel segment of the plurality of channel segments is selected to spectrally position a frequency-interval exhibiting attenuated frequency response on the signaling link such that multiple passbands separated by the frequency-interType: ApplicationFiled: November 12, 2008Publication date: February 10, 2011Inventors: Jared L. Zerbe, Vladimir M. Stojanovic, Ravindranath Kollipara, Wendemagegnehu Beyene, Amir Arnirkhany, Bruno Garlepp