Abstract: The present invention is directed to a method for booting a system-on-chip (SoC) including the steps of directly executing a boot software from an on-chip magnetic random access memory (MRAM) residing on a same semiconductor as the SoC; directly executing an operating system software from an external MRAM by the SoC without loading the operating system into a volatile memory; and directly executing an application software from the external MRAM by the SoC, wherein the external MRAM is coupled to the SoC and is configured for storing the operating system software and the application software.

Abstract: The present invention is directed to a method for booting a system-on-chip (SoC) including the steps of directly executing a boot software from an on-chip magnetic random access memory (MRAM) residing on a same semiconductor as the SoC; directly executing an operating system software from an external MRAM by the SoC without loading the operating system into a volatile memory; and directly executing an application software from the external MRAM by the SoC, wherein the external MRAM is coupled to the SoC and is configured for storing the operating system software and the application software.

Abstract: The present invention is directed to a method for booting a system-on-chip (SoC) including the steps of directly executing a boot software from an on-chip magnetic random access memory (MRAM) residing on a same semiconductor as the SoC; storing an operating system (OS) software and an application software on an external MRAM; directly executing the operating system software from the external MRAM by the SoC without loading the operating system into a volatile memory; directly executing the application software from the external MRAM by the SoC, wherein the external MRAM is coupled to the SoC and is configured for permanently storing the operating system software and the application software.

Abstract: The present invention is directed to a magnetic memory device comprising a memory array structure that includes a first memory array comprising a first plurality of memory cells arranged in rows and columns and a second memory array comprising a second plurality of memory cells arranged in rows and columns. The memory array structure further includes a first multiplexer coupled to a first plurality of first conductive lines with each line connected to a respective column of the first plurality of memory cells; a second multiplexer coupled to a second plurality of first conductive lines with each line connected to a respective column of the second plurality of memory cells; a sense amplifier, whose input is connected to the output of the first multiplexer and the output of the second multiplexer; and a register including a plurality of latches coupled to the sense amplifier via a demultiplexer.

Abstract: The present invention is directed to a magnetic memory device comprising a memory array structure that includes a first memory array comprising a first plurality of memory cells and a second memory array comprising a second plurality of memory cells. Each memory cell of the first and second plurality of magnetic memory cells includes a magnetic memory element and a two-terminal selector coupled in series. The memory array structure further includes a first multiplexer coupled to a third plurality of first conductive lines with each line connected to a respective column of the first plurality of memory cells; a second multiplexer coupled to a fourth plurality of first conductive lines with each line connected to a respective column of the second plurality of memory cells; a sense amplifier, whose input is connected to the output of the first multiplexer and the output of the second multiplexer; and one or more latches coupled to the sense amplifier.

Abstract: The present invention is directed to a computer subsystem that includes a central processing unit (CPU); one or more byte-addressable memory modules having a dual in-line memory module (DIMM) form factor connected to the CPU via a first memory channel; and a master persistent memory module and one or more slave persistent memory modules having the DIMM form factor connected to the CPU via a second memory channel. The master persistent memory module and the one or more slave persistent memory modules are connected in a daisy chain configuration. The one or more slave persistent memory modules receive commands directly from the master persistent memory module.

Abstract: The present invention is directed to a storage device including a storage media and a controller coupled thereto through a high speed interface. The storage media includes one or more byte-addressable persistent memory devices, one or more block-addressable persistent memory devices, a hybrid reserved area spanning at least a portion of the one or more byte-addressable persistent memory devices, and a hybrid user area spanning at least a portion of the one or more block-addressable persistent memory devices. The controller uses the hybrid reserved area to store private data. Each of the one or more byte-addressable persistent memory devices may include one or more magnetic random access memory (MRAM) arrays. Each of the one or more block-addressable persistent memory devices may include one or more NAND flash memory arrays. The high speed interface may be a universal flash storage (UFS) interface that operates in the full-duplex mode.

Abstract: The present invention is directed to a method for booting a system-on-chip (SoC) including the steps of directly executing a boot software from an on-chip magnetic random access memory (MRAM) residing on a same semiconductor as the SoC; storing an operating system (OS) software and an application software on an external MRAM; directly executing the operating system software from the external MRAM by the SoC without loading the operating system into a volatile memory; directly executing the application software from the external MRAM by the SoC, wherein the external MRAM is coupled to the SoC and is configured for permanently storing the operating system software and the application software.

Abstract: The present invention is directed to a computer subsystem that includes a central processing unit (CPU); one or more byte-addressable memory modules having a dual in-line memory module (DIMM) form factor connected to the CPU via a first memory channel; and a master persistent memory module and one or more slave persistent memory modules having the DIMM form factor connected to the CPU via a second memory channel. The master persistent memory module and the one or more slave persistent memory modules are connected in a daisy chain configuration. The one or more slave persistent memory modules receive commands directly from the master persistent memory module.

Abstract: A method of booting a system on chip (SoC) includes using an on-chip MRAM located in the SoC, to store a boot software that includes a start-up software, boot loaders, and kernel and user-personalized information in an on-chip magnetic random access memory (MRAM) located in and residing on the same semiconductor as the SoC. The method further includes directly executing the boot software from the on-chip MRAM by the SoC and directly accessing the user-personalized information from the MRAM by the SoC.

Abstract: The present invention is directed to a storage device including a storage media and a controller coupled thereto through a high speed interface. The storage media includes one or more byte-addressable persistent memory devices, one or more block-addressable persistent memory devices, a hybrid reserved area spanning at least a portion of the one or more byte-addressable persistent memory devices, and a hybrid user area spanning at least a portion of the one or more block-addressable persistent memory devices. The controller uses the hybrid reserved area to store private data. Each of the one or more byte-addressable persistent memory devices may include one or more magnetic random access memory (MRAM) arrays. Each of the one or more block-addressable persistent memory devices may include one or more NAND flash memory arrays. The high speed interface may be a universal flash storage (UFS) interface that operates in the full-duplex mode.

Abstract: The present invention is directed to a memory subsystem including a plurality of memory banks, each of the memory banks including a plurality of memory cells arranged in rows and columns with word-lines connecting to the memory cells along a row direction and bit-lines connecting to the memory cells along a column direction; a sense amplifier module shared by the plurality of memory banks, the sense amplifier module including a plurality of sense amplifiers for sensing resistance of the memory cells; a plurality of memory buffer modules coupled to the sense amplifier module, each of the memory buffer modules including a plurality of memory buffers for storing data from the sense amplifiers; and an input/output (I/O) interface coupled to the memory buffer modules.

Abstract: A server chassis includes add-on cards, interposer elements, and an interconnect subsystem including back planes. The interposer elements are physically connect to the at least two back planes and to the add-on cards therefore electrically coupling the add-on cards to the back planes. The add-on cards are configured in a stacked position such that unobstructed air flows between the add-on cards and through a space defined to be in between the back planes so that unobstructed air flow causes lowering of thermal resistance associated with the server chassis.

Abstract: A storage appliance device includes an interconnect plane, one or more processor bays, with each processor bay including one or more processor nodes and a front-end switch. The storage appliance device further includes one or more storage bays, with each storage bay including one or more storage cards and one or more back-end switches, the interconnect plane causes communication between the one or more processor bays and the one or more storage bays. The front-end switches and back-end switches cause coupling between the processor bay and the storage cards with interfaces that avoid violation of the requirements of a high-speed transceiver being in communication with the storage appliance device.

Abstract: An unified power management scheme for all the idle subsystems during normal mode of operation and power save mode of operation reduces significant power and time during saving and restoring context of System on a chip (SoC). Power management schemes based on subset of manufacturing tests and high speed non-volatile memory provides transparency and shortest latency of entering and exiting power save mode and as a result providing significant power savings and extending battery life. Due to the shortest logic delays in some phases of logic scan, memory BIST and analog BIST, entry procedure and exit procedures from power save mode consume least amount of time with little overhead due to clock switching and power gating procedures. Any part of SoC that can be tested during manufacture using standard procedures of logic scan, memory BIST, analog BIST and boundary scan will be able to enter and exit power save mode and still retain the state.

Abstract: A hybrid non-volatile memory device includes a non-volatile random access memory (NVRAM) having an array of magnetic memory elements, the NVRAM being bit-accessible. The hybrid non-volatile device further includes a non-volatile page-mode memory (PMM) made of resistive memory and organized into pages, the non-volatile PMM being page-accessible. Further included in the hybrid non-volatile memory device is a direct memory access (DMA) engine that is coupled to the NVRAM and the non-volatile PMM and transfers data between the NVRAM and the non-volatile PMM during a DMA operation.

Abstract: A method of booting a system on chip (SoC) includes using an on-chip MRAM located in the SoC, to store a boot software that includes a start-up software, boot loaders, and kernel and user-personalized information in an on-chip magnetic random access memory (MRAM) located in and residing on the same semiconductor as the SoC. The method further includes directly executing the boot software from the on-chip MRAM by the SoC and directly accessing the user-personalized information from the MRAM by the SoC.

Abstract: A memory module includes a bridge controller having a first interface and a second interface. The first interface receives commands and data from a host and the second interface is coupled to one or more memory components. The bridge controller performs multiple-bit error detection and correction on data stored in the one or more memory components.

Abstract: A hybrid non-volatile memory device includes a non-volatile random access memory (NVRAM) having an array of magnetic memory elements, the NVRAM being bit-accessible. The hybrid non-volatile device further includes a non-volatile page-mode memory (PMM) made of resistive memory and organized into pages, the non-volatile PMM being page-accessible. Further included in the hybrid non-volatile memory device is a direct memory access (DMA) engine that is coupled to the NVRAM and the non-volatile PMM and transfers data between the NVRAM and the non-volatile PMM during a DMA operation.