Abstract: A method for performing a division operation in a system includes a) determining an approximate quotient of a numerator value and a denominator value; b) determining an initial error of the approximate quotient; c) determining a quotient adjustment value based on the initial error; d) determining whether to apply the quotient adjustment value to the approximate quotient; e) if the determination at d) is YES, then applying the quotient adjustment value to the approximate quotient; f) determining an iterative error of the approximate quotient; g) updating the quotient adjustment value based on the iterative error; h) repeating acts d) through g) until the determination at d) is NO, thereby determining a final value for the approximate quotient; i) generating an integer quotient based on the final value of the approximate quotient; and j) using the integer quotient with regard to at least one aspect of the system.

Abstract: Disclosed is a computer implemented method, data processing system, and apparatus to respond to detection of a hardware interface error on a system bus, for example, during a concurrent maintenance operation. The service processor may receive an error on the system bus. The error identifies at least one field replaceable unit and may inhibit the suppression of clock signal to the field replaceable unit. The service processor adds an identifier of the field replaceable unit to an eligible Field Replaceable Unit (FRU) list. The service processor recursively adds at least one field replaceable unit that the field replaceable unit depends upon. The service processor suppresses the clock signal to the field replaceable unit. The service processor inhibits tagging the field replaceable unit as unusable for next initial program load.

Abstract: A system for testing or debugging a system including the integrated circuit having an embedded logic analyzer. In one embodiment, the system includes a computing device coupled to the logic analyzer for receiving the at least one output. A user interface run on the computing device assigns an attribute to at least one signal associated with the logic analyzer, determines a new signal or value not provided by the logic analyzer, the new signal or value being based upon the at least one signal as received from the logic analyzer and upon a predetermined definition, and presents the new signal or value to a system user.

Abstract: An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an integrated circuit (IC). The ELA includes an interconnect module to select a trigger signal and/or a sampled signal from the plurality of received signals. A trigger module sets at least one trigger condition and detects if the trigger signal satisfies the at least one trigger condition. When the trigger condition is satisfied, an output module performs at least one task based upon the satisfied at least one trigger condition. If a sampling process is initiated by the output module, the plurality of sampled signals is sampled and may be stored in a memory. The capability of the output module to perform multiple user-defined tasks enhances the debugging capability of the ELA and makes it more versatile.

Abstract: An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment, an integrated circuit includes a logic analyzer having a first input receiving a plurality of signals and an output for providing an indication of a detection, by the logic analyzer, of at least one trigger event; and a built in self test block having a first input for receiving one or more of the signals appearing at the first input of the logic analyzer, a second input coupled to the output of the logic analyzer for selectively enabling the BIST block, the BIST block generating and maintaining a signature based upon the first and second inputs thereof.

Abstract: An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an integrated circuit (IC). The ELA includes an interconnect module to select a trigger signal and/or a sampled signal from the plurality of received signals. A trigger module sets at least one trigger condition and detects if the trigger signal satisfies the at least one trigger condition. When the trigger condition is satisfied, an output module performs at least one task based upon the satisfied at least one trigger condition. If a sampling process is initiated by the output module, the plurality of sampled signals is sampled and may be stored in a memory. The capability of the output module to perform multiple user-defined tasks enhances the debugging capability of the ELA and makes it more versatile.

Abstract: A system and method for fast system recovery that bypasses diagnostic routines by disconnecting failed hardware from the system before rebooting. Failed hardware and hardware that will be affected by removal of the failed hardware of the system are disconnected from the system. The system is restarted, and because the failed hardware is disconnected, diagnostic routines may safely be eliminated from the reboot process.

Abstract: A method for printing of raster data in a media processing device is disclosed. The method includes identifying an attribute of a set of raster lines of the raster data. The method further includes determining at least one print mode from a plurality of print modes based on the attribute. Each print mode of the plurality of print modes is configured to print the set of raster lines of the raster data. Furthermore, the method includes printing the set of raster lines of the raster data in the at least one print mode.

Abstract: A method for dynamically compensating for a faulty pixel in a scan line of a scanner having an image sensor with a plurality of sensor pixels includes generating digitized scan data; processing the digitized scan data to compensate for any faulty pixels of the plurality of sensor pixels to form compensated scan data; processing the compensated scan data to apply offset and gain correction to the compensated scan data to form calibrated scan data; processing the calibrated scan data to adjust the calibrated scan data to compensate for human visual perception to form final scan data; and storing the final scan data in a scanner image memory.

Abstract: The present invention is a toneable conduit that can transmit a signal and that can therefore be readily detected by toning equipment. In addition, the conduit of the invention can be readily coupled with other conduit to provide extended lengths of conduit. The toneable conduit includes an elongate polymeric tube having a wall with an interior surface, an exterior surface, and a predetermined wall thickness. A channel preferably extends longitudinally within the wall of the elongate polymeric tube and a stabilizing rib extends longitudinally along the interior surface of the wall of the elongate polymeric tube and is located radially inward from the channel. A continuous wire is coincident with the channel in the elongate polymeric tube and is preferably coated with a coating composition that prevents the wire from adhering to the polymer melt used to form the elongate polymeric tube.

Abstract: Disclosed is a method for printing a media sheet in a media processing device. The method includes aligning a first portion of a printhead of the media processing device to a print area of the media sheet. The method further includes printing the print area of the media sheet by traversing the printhead over the print area in a first direction. The printing is performed by the first portion. Further, the method includes aligning a second portion of the printhead to the print area by adjusting the media sheet relative to the printhead by an index distance in a direction perpendicular to the first direction. Thereafter, the method includes reprinting the print area by traversing the printhead over the print area in a second direction opposite to the first direction. The reprinting is performed by the second portion.

Abstract: Disclosed is a computer implemented method, data processing system, and apparatus to respond to detection of a hardware interface error on a system bus, for example, during a concurrent maintenance operation. The service processor may receive an error on the system bus. The error identifies at least one field replaceable unit and may inhibit the suppression of clock signal to the field replaceable unit. The service processor adds an identifier of the field replaceable unit to an eligible Field Replaceable Unit (FRU) list. The service processor recursively adds at least one field replaceable unit that the field replaceable unit depends upon. The service processor suppresses the clock signal to the field replaceable unit. The service processor inhibits tagging the field replaceable unit as unusable for next initial program load.

Abstract: A method and an imaging apparatus for reducing print grain effect in an image to be printed by a printing device are disclosed. One or more flat field areas, each comprising at least one flat field pixel, are detected in the image. A color value of each detected flat field pixel in the one or more flat field areas is modified using a unique flat field optimized color lookup table. The modification of the color value of each flat field pixel in the image reduces the print grain effect in the image to be printed by the printing device.

Abstract: An application specific integrated circuit (ASIC) is configured to perform image processing tasks on a printer or other multi-function device. The ASIC includes a processor, a dedicated cache memory, a cache controller and additional Static Random Access Memory (SRAM) normally employed in image processing tasks. This additional SRAM may be dynamically allocated as a cache memory when not otherwise occupied.

Abstract: Digital images that are produced by an image forming device may be processed using an edge enhancement technique to reduce the effects of halftone color depth reductions. For each element in the original image, certain detail elements are classified by examining the magnitude of pixel intensity gradients between elements of interest in a first window applied at each element and other elements in the first window. If a first predetermined condition is satisfied, those elements locations are stored. After halftoning, a morphological filter may be applied to the same element locations in the halftone image to enhance the halftone image.

Abstract: A method of transforming a n-bit data packet to a m-bit data packet with a lookup table. The lookup table includes at least one entry data packet and at least one respective delta value associated with each entry data packet. The method includes the acts of receiving an input data packet having n-bits, indexing the lookup table with at least a portion of the input data packet to obtain one of the at least one entry data packet, and decompressing the obtained entry data packet with the at least one respective delta value associated with the obtained entry data packet, thereby resulting in an output data packet having m-bits. The decompressing act includes using a portion of the input data packet to determine the number of delta values called for decompressing the obtained entry data packet. The method can be used in, for example, an image processor.

Abstract: Error diffusion is performed upon input image data. In one aspect, multiple error diffusion processing elements perform error diffusion on a selected pixel in parallel. In another aspect, the error diffusion logic is integrally formed with a fast local memory in the same electronic device, such as an ASIC. The error data produced by the error diffusion logic for a pixel is buffered in the fast local memory until it is to be used by the error diffusion logic on other pixels. In still another aspect, a first-in-first-out (FIFO) buffer regulates or buffers the color image data between the output of a color conversion system, such as a colorant lookup table, and the input an error diffusion processing element. In yet another aspect, the error diffusion logic has tagging logic that produces and stores an indicator, either in the output data stream itself or in a separate area, to indicate whether a raster contains printable data.

Abstract: A method for dynamically compensating for a faulty pixel in a scan line of a scanner having an image sensor with a plurality of sensor pixels includes generating digitized scan data; processing the digitized scan data to compensate for any faulty pixels of the plurality of sensor pixels to form compensated scan data; processing the compensated scan data to apply offset and gain correction to the compensated scan data to form calibrated scan data; processing the calibrated scan data to adjust the calibrated scan data to compensate for human visual perception to form final scan data; and storing the final scan data in a scanner image memory.

Abstract: A method for performing a division operation in a system includes a) determining an approximate quotient of a numerator value and a denominator value; b) determining an initial error of the approximate quotient; c) determining a quotient adjustment value based on the initial error; d) determining whether to apply the quotient adjustment value to the approximate quotient; e) if the determination at d) is YES, then applying the quotient adjustment value to the approximate quotient; f) determining an iterative error of the approximate quotient; g) updating the quotient adjustment value based on the iterative error; h) repeating acts d) through g) until the determination at d) is NO, thereby determining a final value for the approximate quotient; i) generating an integer quotient based on the final value of the approximate quotient; and j) using the integer quotient with regard to at least one aspect of the system.

Abstract: Lines of input image data are scaled in a first dimension, the one-dimensionally scaled lines are stored in a buffer memory until a sufficient number of lines have been stored to perform scaling equally in two dimensions, and the stored lines are then scaled in a second dimension to produce image data scaled two-dimensionally by a user-selected scaling percentage. A first image scaling method is used to scale the input image data if the user-selected scaling percentage exceeds a predetermined threshold value, such as 50 percent, and a second scaling method is used if the scaling percentage does not exceed the threshold value. The first method can be, for example, linear interpolation, and the second method can be, for example, averaging.