Abstract: In an image capture system having a sensor with a first node and a second node, a method of capturing image data is disclosed. The first node is reset. The second node is reset. An image is collected on the first node. A first pixel value is then transferred from the first node to the second node after a first predetermined time period. The first pixel value and a second pixel value is then provided after a second predetermined time period. An arithmetic operation is performed on the first pixel value and the second pixel value. A system for performing the method is also disclosed.

Abstract: In an image capture system having a sensor with a first node and a second node, a method of capturing image data is disclosed. The first node is reset. The second node is reset. An image is collected on the first node. A first pixel value is then transferred from the first node to the second node after a first predetermined time period. The first pixel value and a second pixel value is then provided after a second predetermined time period. An arithmetic operation is performed on the first pixel value and the second pixel value. A system for performing the method is also disclosed.

Abstract: The CMOS image sensing device includes, on one integrated circuit, a sensor array and compensation circuitry for adjusting signals output from the sensor array to compensate for output signal variations, such as variations caused by voltage, temperature, process or manufacturing variations. The integrated circuit also includes logic circuitry for performing image processing operations on signals output from the sensor array including, for example, pattern recognition operations or filtering operations. In one embodiment, the integrated circuit includes a flash programmable memory array for storing compensation values corresponding to individual pixel elements of the sensor array. In use, the sensor array is illuminated by a flat light source, variations among the magnitude of analog output signals from the elements are detected and corresponding compensation values are calculated. The compensation values are flash programmed into the memory array.

Abstract: A method for securing confidential circuitry from observation by unauthorized inspection, and a secure circuit immune from unauthorized inspection according to the method. In one embodiment, confidential data or circuitry is placed on a face of separate silicon layers, each silicon layer having part of a circuit. Neither silicon layer is intelligible without the other, yet neither can be observed without destroying the other. The two silicon layers are juxtaposed, the face of the first silicon layer flush against and fused to the face of the second silicon layer, the confidential circuits on each silicon layer connecting directly with circuits on the other silicon layer without external connectors. Data stored on each face is erased or destroyed when the silicon layers are separated or one of the silicon layers is destroyed.