Abstract: Circuits and methods characterize a receiver. The circuit includes a decision feedback equalizer (DFE) circuit, a clock and data recovery (CDR) circuit, a data checker, and an eye-scan controller. The DFE circuit generates a filtered signal from the communication signal. The filtered signal is a sum of the communication signal and a variable weighting of a symbol recently sampled from the filtered signal. The CDR circuit samples a sequence of sampled symbols from the filtered signal. The CDR circuit samples the filtered signal at a variable phase relative to a clock signal. The data checker generates an indication of an error in the sequence of sampled symbols. The eye-scan controller varies the variable weighting and the variable phase through multiple value combinations. The eye-scan controller checks for the indication of the error for each of the value combinations.