Abstract: In a master-slave delay type flip-flop, a first transistor transfers the data at the D input to an inverter stage when the clock signal goes low. When the clock signal again goes high, the inverter data is transferred to a second inverter stage which forms the flip-flop Q output. Feedback means have provided for latching the inputs to both the first and second inverter stages. An inverting transistor in one of the feedback paths forms the Q output of the flip-flop. Additional embodiments of the D-type flip-flop circuit include both asynchronous set and reset features.