Abstract: A frequency domain self-synchronization controller for solid state switches is disclosed. The controller analyzes a measured power signal in the frequency domain to identify a frequency domain firing angle and then converts the frequency domain firing angle to a time-domain firing signal command. The time-domain firing signal command is used to fire selected solid state switches of, for example, a static VAR compensator, precisely when the voltage across the selected solid state switches is at or near zero volts, so that the solid state switches are not damaged. The controller also calculates the line voltage level of the power system and in response to the voltage level it automatically executes either a high voltage coarse line conditioning strategy, a high voltage fine line conditioning strategy, a low voltage coarse line conditioning strategy, or a low voltage fine line conditioning strategy.

Abstract: A current source gate drive circuit for simultaneous firing of a set of series or parallel thyristors is described. The circuit includes two current loops, each of which serves as a current transformer primary. Electrically insulating tubes enclose the current loops. Current transformer cores, around which are wound a certain number of secondary turns, surround the current loops, thus magnetically coupling the primary current of the current transformer to the secondary turns. Thyristor gate driver circuits are electrically coupled to the current transformer cores. Each of the thyristor gate driver circuits receives and rectifies ac current signals from the current loops and forms a current pulse train firing signal. Each thyristor gate driver circuit has a corresponding thyristor that is fired by the current pulse train firing signal. The thyristors operate at a high voltage, but are electrically isolated from the current loops by the insulating tubes.

Abstract: The invention is a static VAR compensator (SVC) which provides optimized power factor correction in the presence of resonant line conditions and large amplitude harmonics. A gate drive signal is applied to the solid state devices of the SVC during only a minor fraction of the fundamental cycle to prevent damage to the solid state devices and the capacitors of the SVC, otherwise caused by resonant line conditions or large amplitude harmonics. This relatively short gate drive signal, in the presence of large amplitude harmonics, will force the solid state electronic components to turn-off prematurely. As a result, the capacitors of the SVC provide incomplete reactive power compensation. Feedback from a capacitor polarity circuit is used to determine switched capacitor status at a specific instant in each cycle. A VAR correction controller, responsive to the feedback, executes a control scheme to account for incomplete reactive power compensation.

Abstract: A high power, high frequency inverter has series/parallel resonant inverter elements and employs MOS controlled thyristors (MCTs) in the switching circuit. The resonant inverter elements include a split inductor for reducing peak voltage across the switches. A fault protection circuit cause the power interruption for a short interval before restarting the circuit. High current density is achieved by means of multilayer ceramic chip capacitors and gap ferrite planar inductors.