Abstract: In a multiprocessing machine having several processors which take turns in executing an instruction, processing of two related parameters in one processor takes place at different times so that the parameters are non-coherent for a short time. Program counter addresses have a bit reserved as a flag which is set during non-coherence. When a CPU requests parameter values from the machine, coherency of the parameters is guaranteed by reading the flag as well as the parameters and a CPU software routine determines the coherent values.

Abstract: A timer unit of a microprocessor has a hardware timer limited to the size of its register, and microcode instructions in the timer unit increment a second register when the timer register rolls over to a clear state. The contents of the two registers are concatenated to obtain an extended timer value. A delay in processing the increment of the second register can cause non-coherency of the two registers. By setting a flag when the increment occurs and detecting from the hardware register value whether rollover has occurred, it is logically decided from the flag and the rollover information whether the registers are non-coherent and if so, a correction is made in the value used from one of the registers.