Patents by Inventor Raymond J. Andraka PE

Raymond J. Andraka PE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RECONFIGURABLE REDUCED INSTRUCTION SET COMPUTER PROCESSOR ARCHITECTURE WITH FRACTURED CORES
    Publication number: 20220179823
    Abstract: Systems and methods for reconfiguring a reduced instruction set computer processor architecture are disclosed. Exemplary implementations may: provide a primary processing core consisting of a RISC processor; provide a node wrapper associated with each of the plurality of secondary cores, the node wrapper comprising access memory associates with each secondary core, and a load/unload matrix associated with each secondary core; operate the architecture in a manner in which, for at least one core, data is read from and written to the at least cache memory in a control-centric mode; the secondary cores are selectively partitioned to operate in a streaming mode wherein data streams out of the corresponding secondary core into the main memory and other ones of the plurality of secondary cores.
    Type: Application
    Filed: February 25, 2022
    Publication date: June 9, 2022
    Applicant: Cornami Inc.
    Inventors: Paul L. Master, Frederick Furtek, Martin Alan Franz II, Raymond J. Andraka PE
  • Reconfigurable reduced instruction set computer processor architecture with fractured cores
    Patent number: 11294851
    Abstract: Systems and methods for reconfiguring a reduced instruction set computer processor architecture are disclosed. Exemplary implementations may: provide a primary processing core consisting of a RISC processor; provide a node wrapper associated with each of the plurality of secondary cores, the node wrapper comprising access memory associates with each secondary core, and a load/unload matrix associated with each secondary core; operate the architecture in a manner in which, for at least one core, data is read from and written to the at least cache memory in a control-centric mode; the secondary cores are selectively partitioned to operate in a streaming mode wherein data streams out of the corresponding secondary core into the main memory and other ones of the plurality of secondary cores.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: April 5, 2022
    Assignee: Cornami, Inc.
    Inventors: Paul L. Master, Frederick Furtek, Martin Alan Franz, II, Raymond J. Andraka PE
  • RECONFIGURABLE REDUCED INSTRUCTION SET COMPUTER PROCESSOR ARCHITECTURE WITH FRACTURED CORES
    Publication number: 20190340152
    Abstract: Systems and methods for reconfiguring a reduced instruction set computer processor architecture are disclosed. Exemplary implementations may: provide a primary processing core consisting of a RISC processor; provide a node wrapper associated with each of the plurality of secondary cores, the node wrapper comprising access memory associates with each secondary core, and a load/unload matrix associated with each secondary core; operate the architecture in a manner in which, for at least one core, data is read from and written to the at least cache memory in a control-centric mode; the secondary cores are selectively partitioned to operate in a streaming mode wherein data streams out of the corresponding secondary core into the main memory and other ones of the plurality of secondary cores.
    Type: Application
    Filed: May 4, 2018
    Publication date: November 7, 2019
    Applicant: Cornami Inc.
    Inventors: Paul L. Master, Frederick Furtek, Martin Alan Franz, II, Raymond J. Andraka PE