Abstract: A trench gate field effect device has a semiconductor body (2) with a trench (3) extending into a first major surface (2a) so as to define a regular array of polygonal source cells (4). Each source cell contains a source region (5a,5b) and a body region (6a,6b) with the body regions separating the source regions from a common further region (20). A gate (G) extends within and along said trench (3) for controlling a conduction channel through each of the body regions. Each source cell (4) has a central semiconductor region (60) which is more highly doped than said body regions, is of opposite conductivity type to the further region and forms a diode with the further region. Each source cell (4) has an inner trench boundary (3a) and an outer polygonal trench boundary (3b) with the inner trench boundary bounding a central subsidiary cell (10a) containing the central semiconductor region (60).

Abstract: In the manufacture of semiconductor devices that have an electrode (11,41) in an insulated trench (20), for example a trench-gate MOSFET, process steps are performed to line the trench walls with a lower insulating layer (21) in a lower part of the trench and with a thicker upper insulating layer (22) in an upper part of the trench.

Abstract: A semiconductor device comprises one or more field effect devices (FD) having source and drain regions (5 and 6) spaced apart by a body region (3a). A gate structure (7a, 7b), preferably in a trench (4), controls a conduction channel in a portion (3b) of the body region (3a) between the source and drain regions. The device has one or more mesa structures (100) having end and side walls (100a to 100d). The body region (3a) extends between and meets at least the side walls (100c and 100d) of the mesa structure. The gate structure (7a, 7b) extends along and between the side walls such that the conduction channel accommodating portion (3b) extends along and between the side walls (100c and 100d). The source and drain regions (5 and 6) meet respective end walls (100a and 100b) of the mesa structure and/or its side walls (100c and 100d). At the mesa walls, a source electrode (S) contacts the source region (5) and a drain electrode (D) contacts the drain region (6).

Abstract: In the manufacture of semiconductor devices that have an electrode (11,41) in an insulated trench (20), for example a trench-gate MOSFET, process steps are performed to line the trench walls with a lower insulating layer (21) in a lower part of the trench and with a thicker upper insulating layer (22) in an upper part of the trench.

Abstract: A field-effect semiconductor device, for example a MOSFET of the trench-gate type, comprises side-by-side device cells at a surface (10a) of a semiconductor body (10), and at least one drain connection (41) that extends in a drain trench (40) from the body surface (10a) to an underlying drain region (14a). A channel-accommodating region (15) of the device extends laterally to the drain trench (40). The drain trench (40) extends through the thickness of the channel-accommodating region (15) to the underlying drain region (14a), and the drain connection (41) is separated from the channel-accommodating region (15) by an intermediate insulating layer (24) on side-walls of the drain trench (40). A compact cellular layout can be achieved, with a significant proportion of the total cellular layout area accommodating conduction channels (12). The configuration in a discrete device avoids a need to use a substrate conduction path and so advantageously reduces the ON resistance of the device.

Abstract: Inner trenches (11) of a trenched Schottky rectifier (1a; 1b; 1c; 1d) bound a plurality of rectifier areas (43a) where the Schottky electrode (3) forms a Schottky barrier 43 with a drift region (4). A perimeter trench (18) extends around the outer perimeter of the plurality of rectifier areas (43a). These trenches (11, 18) accommodate respective inner field-electrodes (31) and a perimeter field-electrode (38) that are connected to the Schottky electrode (3). The inner field-electrodes (11) are capacitively coupled to the drift region (4) via dielectric material (21) that lines the inner trenches (11). The perimeter field-electrode (38) is capacitively coupled across dielectric material (28) on the inside wall (18a) of the perimeter trench 18, without acting on any outside wall (18b). Furthermore, the inner and perimeter trenches (11, 18) are closely spaced and the intermediate areas (4a, 4b) of the drift region (4) are lowly doped.