Patents by Inventor Raymond Joy
Raymond Joy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8987827Abstract: A method for fabricating enhanced-mobility pFET devices having channel lengths below 50 nm. Gates for pFETs may be patterned in dense arrays on a semiconductor substrate that includes shallow trench isolation (STI) structures. Partially-enclosed voids in the semiconductor substrate may be formed at source and drain regions for the gates, and subsequently filled with epitaxially-grown semiconductor that compressively stresses channel regions below the gates. Some of the gates (dummy gates) may extend over edges of the STI structures to prevent undesirable faceting of the epitaxial material in the source and drain regions.Type: GrantFiled: May 31, 2013Date of Patent: March 24, 2015Assignees: STMicroelectronics, Inc., International Business Machines Corporation, GLOBALFOUNDRIES, Inc.Inventors: Pietro Montanini, Raymond Joy, Marta Mottura, Henry K. Utomo
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Publication number: 20140353741Abstract: A method for fabricating enhanced-mobility pFET devices having channel lengths below 50 nm. Gates for pFETs may be patterned in dense arrays on a semiconductor substrate that includes shallow trench isolation (STI) structures. Partially-enclosed voids in the semiconductor substrate may be formed at source and drain regions for the gates, and subsequently filled with epitaxially-grown semiconductor that compressively stresses channel regions below the gates. Some of the gates (dummy gates) may extend over edges of the STI structures to prevent undesirable faceting of the epitaxial material in the source and drain regions.Type: ApplicationFiled: May 31, 2013Publication date: December 4, 2014Inventors: Pietro Montanini, Raymond Joy, Marta Mottura, Henry K. Utomo
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Publication number: 20140004677Abstract: Embodiments of the invention include methods of protecting sacrificial gates during raised/source drain and replacement metal gate processes. Embodiments include steps of forming sacrificial gates on a semiconductor substrate, protecting the sacrificial gates with gate seals, forming source/drains near the sacrificial gates without substantially growing semiconductor material on the sacrificial gates, removing the gate seals, and replacing the sacrificial gates with metal gates. In some embodiments, the gate seals are made of a high-k material.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Applicants: GLOBALFOUNDRIES, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ying Li, Raymond Joy, Yong Meng Lee
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Publication number: 20120255586Abstract: An first example method and apparatus for etching and cleaning a substrate comprises device with a first manifold and a second manifold. The first manifold has a plurality of nozzles for dispensing chemicals onto the substrate. The second manifold is attached to a vacuum source and/or a dry air/gas source. A second example embodiment is a wafer cleaning device and method that uses a manifold with capillary jet nozzles and a liquid capillary jet stream to clean substrates.Type: ApplicationFiled: April 11, 2012Publication date: October 11, 2012Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Boon Meng SEAH, Bei Chao ZHANG, Raymond JOY, Shao Beng LAW, John SUDIJONO, Liang Choo HSIA
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Patent number: 8177993Abstract: An first example method and apparatus for etching and cleaning a substrate comprises device with a first manifold and a second manifold. The first manifold has a plurality of nozzles for dispensing chemicals onto the substrate. The second manifold is attached to a vacuum source and/or a dry air/gas source. A second example embodiment is a wafer cleaning device and method that uses a manifold with capillary jet nozzles and a liquid capillary jet stream to clean substrates.Type: GrantFiled: November 5, 2006Date of Patent: May 15, 2012Assignee: GLOBALFOUNDRIES Singapore Pte LtdInventors: Boon Meng Seah, Bei Chao Zhang, Raymond Joy, Shao Beng Law, John Sudijono, Liang Choo Hsia
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Patent number: 7601607Abstract: An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.Type: GrantFiled: May 15, 2006Date of Patent: October 13, 2009Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Wuping Liu, Raymond Joy, Beichao Zhang, Liang Choo Hsia, Boon Meng Seah, Shyam Pal
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Publication number: 20080105653Abstract: An first example method and apparatus for etching and cleaning a substrate comprises device with a first manifold and a second manifold. The first manifold has a plurality of nozzles for dispensing chemicals onto the substrate. The second manifold is attached to a vacuum source and/or a dry air/gas source. A second example embodiment is a wafer cleaning device and method that uses a manifold with capillary jet nozzles and a liquid capillary jet stream to clean substrates.Type: ApplicationFiled: November 5, 2006Publication date: May 8, 2008Inventors: Boon Meng Seah, Bei Chao Zhang, Raymond Joy, Shao Beng Law, John Sudijono, Liang Choo Hsia
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Patent number: 7352064Abstract: Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.Type: GrantFiled: November 4, 2004Date of Patent: April 1, 2008Assignee: International Business Machines CorporationInventors: Nicholas C. M. Fuller, Timothy J. Dalton, Raymond Joy, Yi-hsiung Lin, Chun Hui Low
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Publication number: 20070264820Abstract: An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.Type: ApplicationFiled: May 15, 2006Publication date: November 15, 2007Inventors: Wuping Liu, Raymond Joy, Beichao Zhang, Liang Hsia, Boon Seah, Shyam Pal
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Publication number: 20060094230Abstract: Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.Type: ApplicationFiled: November 4, 2004Publication date: May 4, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nicholas Fuller, Timothy Dalton, Raymond Joy, Yi-hsiung Lin, Chun Low
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Patent number: 6548413Abstract: A new method of etching metal lines with reduced microloading effect is described. Semiconductor device structures are provided in and on a semiconductor substrate and covered with an insulating layer. A barrier metal layer is deposited overlying the insulating layer and a metal layer is deposited overlying the barrier metal layer. The metal layer is covered with a photoresist mask wherein there are both wide spaces and narrow spaces between portions of the photoresist mask. The metal layer is etched away where it is not covered by the photoresist mask wherein the barrier metal layer is reached within the wide spaces while some of the metal layer remains within the narrow spaces. The metal layer remaining within the narrow spaces is selectively etched away. Thereafter, the barrier metal layer not covered by the photoresist mask is etched away wherein the insulating layer is reached within the wide spaces while some of the barrier metal layer remains within the narrow spaces.Type: GrantFiled: March 26, 1998Date of Patent: April 15, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Paul Kwok Keung Ho, Thomas Schulue, Raymond Joy, Wai Lok Lee, Ramasamy Chockalingam, Ba Tuan Pham, Premachandran Vayalakkara
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Patent number: 6271115Abstract: An improved method for removing a photoresist mask from an etched aluminum pattern after etching the pattern in a chlorine containing plasma has been developed. The method is a five step process, in which the first step is in a microwave generated plasma containing O2 and H2O; the second step is in a microwave generated plasma containing O2 and N2; the third step is in a microwave generated plasma containing H2O; the fourth step is in a microwave generated plasma containing O2 and N2; and the fifth step is in a microwave generated plasma containing H2O. The first step which initiates removal of photoresist while simultaneously beginning the passivation process causes residue-free removal of photoresist following etching of aluminum or aluminum-copper layers in chlorine bearing etchants.Type: GrantFiled: June 26, 2000Date of Patent: August 7, 2001Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Wen Jun Liu, Simon Chooi, Mei Sheng Zhou, Raymond Joy