Abstract: A phase-locked loop (PLL) frequency synthesizer having an analog, out-of-band component path and a digital, in-band component path to provide frequency modulation (FM) of the synthesized output signal is described. The in-band FM component is octave scaled by an analog scaling means and coupled to an analog-to-digital converter to provide a digital number to be decade added to the PLL divide number to change the PLL frequency in response to the in-band FM signal. The out-of-band FM component is also scaled and applied to a loop summing node and summed with the PLL error signal to vary the PLL frequency. The scaling in both the in-band component path and out-of-band component path is equalized to provide a flat frequency response. Additional, the in-band component is scaled to allow use of the analog-to-digital converter over its maximum range to maintain a high signal-to-noise ratio.

Abstract: Signal generating apparatus including a phase-locked loop (PLL) utilizing a voltage-controlled oscillator (VCO) and a frequency-locked loop (FLL) to generate an output signal whose frequency jumps from one value to another in a selectable sequence. The signal generator further includes a delay line discriminator to provide an error signal to compensate for FM noise in the VCO. The frequency-locked loop is implemented by utilizing the FM error signal from the delay line discriminator to stabilize the center frequency of the VCO. The inherent wide bandwidth of the FLL provides a fast settling time when the loop is switched to a new frequency. In a learn mode, the gain parameters of the loop are determined and stored each of a plurality of frequencies. The gain parameters and a corresponding pretune signal for each selected frequencies are the applied to the FLL in a selectable sequence to provide a fast-switching signal generator.

Abstract: A programmable divide-by-N phase-locked loop having a pulse incrementor circuit and a single sideband mixer circuit embedded in the loop feedback path is disclosed. In each disclosed arrangement, one input port of the single sideband mixer receives the signals supplied by the phase-locked loop voltage controlled oscillator and, depending upon whether the mixer employed is configured for supplying an upper sideband signal or a lower sideband signal, either increases or decreases the frequency of the phase-locked loop feedback signal by a factor f.sub.s, where f.sub.s is the frequency of a control signal applied to the second input port of the signal sideband mixer. The pulse incrementor circuit receives the signal supplied by the single sideband mixer and, depending on whether the pulse incrementor is configured for deleting signal pulses or adding signal pulses, either decreases or increases the average frequency of the signals supplied to the phase-locked loop programmable divider by a factor f.sub.

Abstract: A frequency synthesizer utilizing a series of individual frequency generating circuits, each circuit containing two phase locked loops, the operation of the loops being under the control of a computer which translates the value of the desired frequency into specific digital commands for the individual circuits. In conjunction with this series of frequency generating circuits is a divider network to which the output of the last frequency generating circuit is applied. The divider network utilizes the generated range of frequencies either directly, routing them to the output, or divides the applied frequency, depending on the particular frequency to be supplied at the output.