Abstract: An encoder/decoder is disclosed which is operative to convert an 8 bit value to a ten bit serial run length limited code for transmission over a serial data link. The encoding technique maintains DC balance within 2 bits over a single ten bit word and compensates for DC imbalance by inverting selected words in the transmission sequence to correct for a DC imbalance resulting from the transmission of a prior unbalanced word. One or more encoding lookup tables are employed at the encoder to map each byte into a ten bit run length limited code for serialization and transmission over the serial data link. A second decoding lookup table is employed at the decoder to map the received 10 bit run length limited code into the original 8 bit value.

Abstract: A method and apparatus for providing buffer state accounting at a link level, otherwise known as link flow control, in addition to flow control at the virtual connection level. Link flow control enables receiver cell buffer sharing while maintaining per-connection bandwidth with lossless cell transmission. High link level update frequency is enabled without a significant sacrifice in overall link forward bandwidth. A higher and thus more efficient utilization of receiver cell buffers is achieved.

Abstract: An encoder/decoder is disclosed which is operative to convert an 8 bit value to a ten bit serial run length limited code for transmission over a serial data link. The encoding technique maintains DC balance within 2 bits over a single ten bit word and compensates for DC imbalance by inverting selected words in the transmission sequence to correct for a DC imbalance resulting from the transmission of a prior unbalanced word. One or more encoding lookup tables are employed at the encoder to map each byte into a ten bit run length limited code for serialization and transmission over the serial data link. A second decoding lookup table is employed at the decoder to map the received 10 bit run length limited code into the original 8 bit value.

Abstract: Methods and apparatus for scheduling cell transmission over a network link by a switch. The switch includes a plurality of queues associated with each link. Lists of queues are maintained for each link. In one embodiment, each link is associated with more than one type of list (with the list type corresponding to a scheduling category) and more than one prioritized list of each type (with the priority of the list corresponding to a quality of service). The scheduling lists are accessed to permit cell transmission from a queue contained therein in a predetermined sequence as a function of scheduling category, priority within a particular scheduling category and whether the bandwidth requirement for the particular scheduling category has been met. With this arrangement, maximum permissible delay requirements for each scheduling category are met.

Abstract: A method and apparatus is disclosed for allocating bandwidth within a network switch having a plurality of input ports coupled to a plurality of output ports through a switch fabric to assure that a minimum bandwidth is allocated for predetermined scheduling lists. A switch allocation table is provided for each of a plurality of input ports. Each switch allocation table is organized as a circular table which is sequentially indexed via an associated index counter. Respective entries in the switch allocation table comprise scheduling list numbers which serve to identify cells requiring switch bandwidth. The respective index counters are synchronized such that all switch allocation tables have a corresponding entry selected. The amount of bandwidth and delay through the network switch is controlled for each of the scheduling lists based upon the number and spacing of entries in the respective switch allocation table.

Abstract: A method and apparatus for providing buffer state accounting at a link level, otherwise known as link flow control, in addition to flow control at the virtual connection level. Link flow control enables receiver cell buffer sharing while maintaining perconnection bandwidth with lossless cell transmission. High link level update frequency is enabled without a significant sacrifice in overall link forward bandwidth. A higher and thus more efficient utilization of receiver cell buffers is achieved.

Abstract: A linked-list structure and method for use in an ATM network switch capable of adaptively providing highly efficient, and thus low cost, integrated services therein. The linked-list structure involves the creation of a list having pointers to a subsequent linked list as list entries. Within the subsequent linked list, each entry can be a pointer to a further linked list. The structure can be expanded to further levels of linked lists as required. Bandwidth distribution is thus achieved among list members at each level. The linked-list structure is employed in the present switch, which includes an input port processor, a bandwidth arbiter, and an output port processor, for switch bandwidth scheduling for both point-to-point, multipoint-to-point and point-to-multipoint cell transfers from the input port processor, and for output link scheduling at the output port processor.

Abstract: A method and apparatus for providing buffer state accounting at a link level, otherwise known as link flow control, in addition to flow control at the virtual connection level. Link flow control enables receiver cell buffer sharing while maintaining per-connection bandwidth with lossless cell transmission. High link level update frequency is enabled without a significant sacrifice in overall link forward bandwidth. A higher and thus more efficient utilization of receiver cell buffers is achieved.

Abstract: Writeback transactions from a processor and cache are fed to a main memory through a writeback queue, and non-writeback transactions from the processor and cache are fed to the main memory through a non-writeback queue. When a cache error is detected, an error transition mode (ETM) is entered that provides limited use of the data in the cache; a read or write request for data not owned in the cache is made to the main memory instead of the cache, even when the data is valid in the cache, although owned data is read from the cache. In ETM, when the processor makes a first write request to data not owned in the cache followed by a second write request to data owned in the cache, write data of the first write request is prevented from being received by the main memory after write data of the second request while permitting writeback of the data owned by the cache.