Patents by Inventor Raymond M. Higgs
Raymond M. Higgs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11112928Abstract: According to one or more embodiments of the present invention, a computer-implemented method includes receiving a request to update a layout of a user interface being rendered. The method further includes receiving a user input for an element of the user interface. The method further includes determining whether the user input is received within a predetermined duration since receiving the request to update the layout. The method further includes, based on a determination that the user input is received after completion of the predetermined duration, accepting the user input. The method further includes, based on a determination that the user input is received prior to completion of the predetermined duration, rejecting the user input.Type: GrantFiled: October 18, 2018Date of Patent: September 7, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Raymond M. Higgs, Christopher Colonna, Luke Hopkins
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Patent number: 10949307Abstract: Technical solutions are described for executing a computer instruction including an asynchronous operation. An example method includes computing parameters associated with the asynchronous operation, and transmitting a command for executing the asynchronous operation by an external device. The method also includes intercepting and storing, by an interface logic controller, the parameters associated with the asynchronous operation into one or more log registers. The method also includes receiving a response to the asynchronous operation. In response to the asynchronous operation being a success, executing a next instruction by the processing element. In response to the asynchronous operation being a failure, a processing element accesses the parameters from the log registers, and restarts the asynchronous operation using the parameters from the one or more log registers.Type: GrantFiled: March 20, 2019Date of Patent: March 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Raymond M. Higgs, Luke M. Hopkins, Mushfiq U. Saleheen
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Patent number: 10664276Abstract: Technical solutions are described for a supervisory processor to pass an out-of-band communication to a target processor in a multiprocessor system. For example, a first processor in a multi-processor system includes a register configured to store a command from a second processor of the multi-processor system, and to store a response to the command from the second processor. The first processor determines that the second processor has issued the command for execution by the first processor based on a first portion of the register being set to a first state, which is a predetermined state. The first processor also, responsively, reads the command from the second processor by parsing a second portion of the register. The first processor includes executes the command and stores the response for the command in the register.Type: GrantFiled: September 28, 2016Date of Patent: May 26, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Raymond M. Higgs, Luke M. Hopkins, Mushfiq U. Saleheen, Gabriel M. Tarr
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Publication number: 20200125217Abstract: According to one or more embodiments of the present invention, a computer-implemented method includes receiving a request to update a layout of a user interface being rendered. The method further includes receiving a user input for an element of the user interface. The method further includes determining whether the user input is received within a predetermined duration since receiving the request to update the layout. The method further includes, based on a determination that the user input is received after completion of the predetermined duration, accepting the user input. The method further includes, based on a determination that the user input is received prior to completion of the predetermined duration, rejecting the user input.Type: ApplicationFiled: October 18, 2018Publication date: April 23, 2020Inventors: Raymond M. Higgs, Christopher Colonna, Luke Hopkins
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Patent number: 10627888Abstract: Embodiments are directed to a method of optimizing power consumption in an electrical device. The method includes receiving, by a processor, instructions to enter a wait state, and identifying, by the processor, a parameter associated with the instructions to enter a wait state. The method continues with initiating, by the processor, instructions to enter a low-power mode based on the parameter, initiating, by the processor, instructions to exit a low-power mode based on the parameter, and providing, via a user interface, a user with notice of a current state of the processor. The parameter includes runtime information, instructional information, and scheduled operations.Type: GrantFiled: January 30, 2017Date of Patent: April 21, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Raymond M. Higgs, Luke M. Hopkins, Mushfiq Saleheen
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Patent number: 10409750Abstract: An aspect of obtaining optical signal health data in a SAN includes receiving, by a computer processor, a request for data corresponding to current operational characteristics of elements of a storage area network to which a host system computer has access. A further aspect includes instantiating, by the computer processor, a virtual host bus adapter interface on the host system computer, transmitting, via the virtual host bus adapter interface, the request to the elements in the portion of the storage area network, aggregating data received from each of the elements, and displaying the aggregated data via the computer processor.Type: GrantFiled: July 11, 2016Date of Patent: September 10, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ralph Friedrich, Raymond M. Higgs, George P. Kuch, Elizabeth A. Moore, Richard M. Sczepczenski
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Publication number: 20190220362Abstract: Technical solutions are described for executing a computer instruction including an asynchronous operation. An example method includes computing parameters associated with the asynchronous operation, and transmitting a command for executing the asynchronous operation by an external device. The method also includes intercepting and storing, by an interface logic controller, the parameters associated with the asynchronous operation into one or more log registers. The method also includes receiving a response to the asynchronous operation. In response to the asynchronous operation being a success, executing a next instruction by the processing element. In response to the asynchronous operation being a failure, a processing element accesses the parameters from the log registers, and restarts the asynchronous operation using the parameters from the one or more log registers.Type: ApplicationFiled: March 20, 2019Publication date: July 18, 2019Inventors: Raymond M. Higgs, Luke M. Hopkins, Mushfiq U. Saleheen
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Patent number: 10346311Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.Type: GrantFiled: November 7, 2017Date of Patent: July 9, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr
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Patent number: 10310996Abstract: A system for managing one or more queues in a multi-processor environment includes a memory configured to be accessed by a plurality of processing elements, and a queue manager disposed in communication with a plurality of processors and with the memory, the queue manager configured to control a queue in the memory, the queue including a plurality of queue elements, the queue manager configured to intercept a message from a processing element of the plurality of processing elements and perform one or more queuing operations on the queue based on the message. The system also includes a dynamically configurable queue full value maintained by the queue manager, the queue full value being a threshold value that specifies a maximum number of the queue elements that can be written to before a queue full condition is detected, the maximum number based on a number of processing elements.Type: GrantFiled: May 31, 2017Date of Patent: June 4, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Kirk Pospesel
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Patent number: 10303627Abstract: A system for managing one or more queues in a multi-processor environment includes a memory configured to be accessed by a plurality of processing elements, and a queue manager disposed in communication with a plurality of processors and with the memory, the queue manager configured to control a queue in the memory, the queue including a plurality of queue elements, the queue manager configured to intercept a message from a processing element of the plurality of processing elements and perform one or more queuing operations on the queue based on the message. The system also includes a dynamically configurable queue full value maintained by the queue manager, the queue full value being a threshold value that specifies a maximum number of the queue elements that can be written to before a queue full condition is detected, the maximum number based on a number of processing elements.Type: GrantFiled: November 2, 2017Date of Patent: May 28, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Kirk Pospesel
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Patent number: 10248509Abstract: Technical solutions are described for executing a computer instruction including an asynchronous operation. An example method includes computing parameters associated with the asynchronous operation, and transmitting a command for executing the asynchronous operation by an external device. The method also includes intercepting and storing, by an interface logic controller, the parameters associated with the asynchronous operation into one or more log registers. The method also includes receiving a response to the asynchronous operation. In response to the asynchronous operation being a success, executing a next instruction by the processing element. In response to the asynchronous operation being a failure, a processing element accesses the parameters from the log registers, and restarts the asynchronous operation using the parameters from the one or more log registers.Type: GrantFiled: November 16, 2016Date of Patent: April 2, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Raymond M. Higgs, Luke M. Hopkins, Mushfiq U. Saleheen
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Patent number: 10210095Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.Type: GrantFiled: July 6, 2017Date of Patent: February 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr
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Patent number: 10210106Abstract: A system for managing one or more queues in a multi-processor environment includes a queue manager disposed in communication with a plurality of processors and a memory shared by the plurality of processors, and a queue configured to be controlled by the queue manager, the queue including independent and discrete queue elements and having a starting location specified by a base address, the queue manager having one or more dynamically configurable parameters, the one or more dynamically configurable parameters including a size of each of the queue elements. The queue manager is configured to perform receiving a message from a processor of the plurality of processors, the message including an operation address specifying a fixed storage location in the memory and a request related to accessing the memory, selecting the queue based on the operation address, and performing a queuing operation on the queue based on the request.Type: GrantFiled: March 15, 2017Date of Patent: February 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven G. Aden, Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr
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Publication number: 20190012268Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.Type: ApplicationFiled: July 6, 2017Publication date: January 10, 2019Inventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr
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Publication number: 20190012269Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.Type: ApplicationFiled: November 7, 2017Publication date: January 10, 2019Inventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr
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Publication number: 20180349300Abstract: A system for managing one or more queues in a multi-processor environment includes a memory configured to be accessed by a plurality of processing elements, and a queue manager disposed in communication with a plurality of processors and with the memory, the queue manager configured to control a queue in the memory, the queue including a plurality of queue elements, the queue manager configured to intercept a message from a processing element of the plurality of processing elements and perform one or more queuing operations on the queue based on the message. The system also includes a dynamically configurable queue full value maintained by the queue manager, the queue full value being a threshold value that specifies a maximum number of the queue elements that can be written to before a queue full condition is detected, the maximum number based on a number of processing elements.Type: ApplicationFiled: November 2, 2017Publication date: December 6, 2018Inventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Kirk Pospesel
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Publication number: 20180349299Abstract: A system for managing one or more queues in a multi-processor environment includes a memory configured to be accessed by a plurality of processing elements, and a queue manager disposed in communication with a plurality of processors and with the memory, the queue manager configured to control a queue in the memory, the queue including a plurality of queue elements, the queue manager configured to intercept a message from a processing element of the plurality of processing elements and perform one or more queuing operations on the queue based on the message. The system also includes a dynamically configurable queue full value maintained by the queue manager, the queue full value being a threshold value that specifies a maximum number of the queue elements that can be written to before a queue full condition is detected, the maximum number based on a number of processing elements.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Inventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Kirk Pospesel
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Publication number: 20180267909Abstract: A system for managing one or more queues in a multi-processor environment includes a queue manager disposed in communication with a plurality of processors and a memory shared by the plurality of processors, and a queue configured to be controlled by the queue manager, the queue including independent and discrete queue elements and having a starting location specified by a base address, the queue manager having one or more dynamically configurable parameters, the one or more dynamically configurable parameters including a size of each of the queue elements. The queue manager is configured to perform receiving a message from a processor of the plurality of processors, the message including an operation address specifying a fixed storage location in the memory and a request related to accessing the memory, selecting the queue based on the operation address, and performing a queuing operation on the queue based on the request.Type: ApplicationFiled: March 15, 2017Publication date: September 20, 2018Inventors: Steven G. Aden, Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr
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Patent number: 10061600Abstract: A control component of a computing environment activates a virtual adapter hosted on a physical adapter of a host system of the computing environment. The virtual adapter is for use by a guest of the host system in performing data input and output. The activating activates the virtual adapter absent involvement of the guest. Based on activating the virtual adapter, the control component obtains configuration information of the activated virtual adapter from the physical adapter, the configuration information generated based on the activating. The control component ascertains a configuration of the activated virtual adapter based on the obtained configuration information.Type: GrantFiled: December 14, 2017Date of Patent: August 28, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ralph Friedrich, Raymond M. Higgs, George P. Kuch, Elizabeth A. Moore, Johnathon R. Pandich, Richard M. Sczepczenski
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Patent number: 10042653Abstract: A control component of a computing environment activates a virtual adapter hosted on a physical adapter of a host system of the computing environment. The virtual adapter is for use by a guest of the host system in performing data input and output. The activating activates the virtual adapter absent involvement of the guest. Based on activating the virtual adapter, the control component obtains configuration information of the activated virtual adapter from the physical adapter, the configuration information generated based on the activating. The control component ascertains a configuration of the activated virtual adapter based on the obtained configuration information.Type: GrantFiled: December 14, 2017Date of Patent: August 7, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ralph Friedrich, Raymond M. Higgs, George P. Kuch, Elizabeth A. Moore, Johnathon R. Pandich, Richard M. Sczepczenski