Abstract: A compiling method compiles an object program to be executed by a processor having a plurality of execution units operable in parallel. In the method a first availability chain is created from a producer instruction (p1), scheduled for execution by a first one of the execution units (20: AGU), to a first consumer instruction (c1), scheduled for execution by a second one of the execution units (22: EXU) and requiring a value produced by the said producer instruction. The first availability chain comprises at least one move instruction (mv1-mv3) for moving the required value from a first point (20: ARF) accessible by the first execution unit to a second point (22: DRF) accessible by the second execution unit.

Abstract: A compiling method compiles an object program to be executed by a processor having a plurality of execution units operable in parallel. In the method a first availability chain is created from a producer instruction (p1), scheduled for execution by a first one of the execution units (20: AGU), to a first consumer instruction (c1), scheduled for execution by a second one of the execution units (22: EXU) and requiring a value produced by the said producer instruction. The first availability chain comprises at least one move instruction (mv1-mv3) for moving the required value from a first point (20: ARF) accessible by the first execution unit to a second point (22: DRF) accessible by the second execution unit.

Abstract: A compiling method compiles an object program to be executed by a processor having a plurality of execution units operable in parallel. In the method a first availability chain is created from a producer instruction (p1), scheduled for execution by a first one of the execution units (20: AGU), to a first consumer instruction (c1), scheduled for execution by a second one of the execution units (22: EXU) and requiring a value produced by the said producer instruction. The first availability chain comprises at least one move instruction (mv1-mv3) for moving the required value from a first point (20: ARF) accessible by the first execution unit to a second point (22: DRF) accessible by the second execution unit.

Abstract: A compiling method compiles an object program to be executed by a processor having a plurality of execution units operable in parallel. In the method a first availability chain is created from a producer instruction (p1), scheduled for execution by a first one of the execution units (20: AGU), to a first consumer instruction (c1), scheduled for execution by a second one of the execution units (22: EXU) and requiring a value produced by the said producer instruction. The first availability chain comprises at least one move instruction (mv1-mv3) for moving the required value from a first point (20: ARF) accessible by the first execution unit to a second point (22: DRF) accessible by the second execution unit.

Abstract: A compiling method compiles an object program to be executed by a processor having a plurality of execution units operable in parallel. A first availability chain is created from a producer instruction (p1) to a first consumer instruction (c1), when the execution of the instruction requires a value produced by the producer instruction. The first availability chain includes at least one move instruction (mv1-mv3) for moving the required value from a first point (20: ARF) accessible by the producer execution unit to a second point (22: DRF) accessible by a first consumer execution unit. When a second consumer instruction (c2), also requiring the same value, is scheduled for execution by an execution unit (23: EXU) other than the first consumer execution unit, at least part of the first availability chain is reused to move the required value to a point (23: DRF) accessible by that other execution unit.

Abstract: A processor is capable of executing a software-pipelined loop. A plurality of registers (20) store values produced and consumed by executed instructions. A register renaming unit (32) renames the registers during execution of the loop. In the event that a software-pipelined loop requires zero iterations, the registers are renamed in a predetermined way to make the register allocation consistent with that which occurs in the normal case in which the loop has one or more iterations. This is achieved by carrying out an epilogue phase only of the loop with the instructions in the loop schedule turned off so that their results do not commit. The issuance of the instructions in the epilogue phase brings about the predetermined renaming automatically. The number of epilogue iterations may be specified in a loop instruction used to start up the loop.

Abstract: A computer display system and method for displaying a sequence of video images in a portion of a graphic display. The video images are provided to the system along with a first set commands that define the size of the images relative to the display as well as their position for insertion into the display. A command modifier, internal to the display system modifies the first set of video image size/position commands to produce a second set of commands. These modifications are performed by the command modifier in response to signals such as from user-generated commands. The second set of video image size/position commands are then forwarded, respectively to a scaling unit and a image insertion unit. The scaling unit scales the video image signals based on the size commands contained in the second set of commands. The insertion unit inserts the scaled video image sequence into the graphics display based on the second set of commands.