Abstract: Disclosed implementations relate to using mutual constraint satisfaction to sample from different stochastic processes and identify coherent inferences across domains. In some implementations, a first domain representation of a semantic concept may be used to conditionally sample a first set of candidate second domain representations of the semantic concept from a first stochastic process. Based on second domain representation(s) of the first set, candidate third domain representations of the semantic concept may be conditionally sampled from a second stochastic process. Based on candidate third domain representation(s), a second set of candidate second domain representations of the semantic concept may be conditionally sampled from a third stochastic process. Pairs of candidate second domain representations sampled across the first and second sets may be evaluated. Based on the evaluation, second domain representation(s) of the semantic concept are selected, e.g., as input for a downstream computer process.

Abstract: Particular aspects provide a garment for simulating chronic obstructive pulmonary disease (COPD), comprising a particularly efficacious combination of a thorax-constricting garment portion, and a diaphragm-impeding garment portion, along with an optional restrictive airway mask. The thorax-constricting portion has a frontal abdominal-thoracic plate member and tensioning means extendible around a wearer's thoracic circumference to provide for constrictive thoracic-abdominal tensioning. The diaphragm-impeding portion has a projection (e.g., weighted projection or pouch) projecting away from the wearer-proximal surface of the frontal plate member, which is operative with the thorax-constricting portion to simultaneously constrict thorax expansion while impeding diaphragm contraction and downward movement.

Abstract: An output circuit for a TTL-CMOS integrated circuit that comprises an output stage with two P MOS and N MOS transistors in parallel, which are connected in cascade with an N MOS enabling transistor between the power supply and the reference voltages. The output stage connected by means of a validation signal TRISB and of P and N MOS transistors delivers an output signal representing the input logic variable to the common point between the P MOS transistor and enabling transistor. A first circuit allows switching of the P MOS transistor by an intermediate switching control signal TRISP and a third circuit allows switching of the N MOS transistor, the circuit operating in mode of feedback of the switching control of the P MOS transistor, the controls being applied successively in order to generate an intermediate switching level belonging to the high logic level.