Patents by Inventor Raymond Nijssen
Raymond Nijssen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230409201Abstract: A conflict-free parallel radix sorting algorithm, and devices and systems implementing this algorithm, schedules memory copies of data elements of a large dataset so that there is always a single copy to each target memory each cycle of operation for the system implementing the algorithm. The conflict-free parallel radix sorting algorithm eliminates memory copying conflicts in copying data elements from different source memories to the same target memory and in this way maintains maximum throughput for the copying of data elements from source memories to target memories, reducing the time required to sort the data elements of the large dataset.Type: ApplicationFiled: January 13, 2023Publication date: December 21, 2023Inventors: Marcel Van der Goot, Raymond Nijssen, Christopher C. LaFrieda
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Publication number: 20230325334Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.Type: ApplicationFiled: June 13, 2023Publication date: October 12, 2023Inventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
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Patent number: 11734216Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.Type: GrantFiled: February 18, 2022Date of Patent: August 22, 2023Assignee: Achronix Semiconductor CorporationInventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
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Publication number: 20230244446Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.Type: ApplicationFiled: March 23, 2023Publication date: August 3, 2023Inventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
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Patent number: 11650792Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.Type: GrantFiled: January 6, 2022Date of Patent: May 16, 2023Assignee: Achronix Semiconductor CorporationInventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
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Publication number: 20220214990Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.Type: ApplicationFiled: February 18, 2022Publication date: July 7, 2022Inventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
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Publication number: 20220129244Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.Type: ApplicationFiled: January 6, 2022Publication date: April 28, 2022Inventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
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Patent number: 11288220Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.Type: GrantFiled: October 18, 2019Date of Patent: March 29, 2022Assignee: Achronix Semiconductor CorporationInventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
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Patent number: 11256476Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.Type: GrantFiled: August 8, 2019Date of Patent: February 22, 2022Assignee: Achronix Semiconductor CorporationInventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
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Publication number: 20210117356Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.Type: ApplicationFiled: October 18, 2019Publication date: April 22, 2021Inventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
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Patent number: 10963221Abstract: In some example embodiments a logical block comprising twelve inputs and two six-input lookup tables (LUTs) is provided, wherein four of the twelve inputs are provided as inputs to both of the six-input lookup tables. This configuration supports efficient field programmable gate array (FPGA) implementation of multipliers. Each six-input LUT comprises two five-input lookup tables (LUT5s) that are used to form Booth encoding multiplier building blocks. The five inputs to each LUT5 are two bits from a multiplier and three Booth-encoded bits from a multiplicand. By assembling building blocks, multipliers of arbitrary size may be formed.Type: GrantFiled: February 27, 2020Date of Patent: March 30, 2021Assignee: Achronix Semiconductor CorporationInventors: Daniel Pugh, Raymond Nijssen
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Publication number: 20210042087Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.Type: ApplicationFiled: August 8, 2019Publication date: February 11, 2021Inventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
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Publication number: 20200373925Abstract: A tile of an FPGA fuses memory and arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased. The arithmetic unit accesses inputs from a combination of: the switch fabric, the memory circuit, a second memory circuit of the tile, and a cascade input. In some example embodiments, the routing of the connections on the tile is based on post-fabrication configuration. In one configuration, all connections are used by the memory circuit, allowing for higher bandwidth in writing or reading the memory. In another configuration, all connections are used by the arithmetic circuit.Type: ApplicationFiled: July 28, 2020Publication date: November 26, 2020Inventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton
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Patent number: 10790830Abstract: A tile of an FPGA fuses memory and arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased. The arithmetic unit accesses inputs from a combination of: the switch fabric, the memory circuit, a second memory circuit of the tile, and a cascade input. In some example embodiments, the routing of the connections on the tile is based on post-fabrication configuration. In one configuration, all connections are used by the memory circuit, allowing for higher bandwidth in writing or reading the memory. In another configuration, all connections are used by the arithmetic circuit.Type: GrantFiled: May 20, 2019Date of Patent: September 29, 2020Assignee: Achronix Semiconductor CorporationInventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton
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Publication number: 20200195951Abstract: In some example embodiments a logical block comprising twelve inputs and two six-input lookup tables (LUTs) is provided, wherein four of the twelve inputs are provided as inputs to both of the six-input lookup tables. This configuration supports efficient field programmable gate array (FPGA) implementation of multipliers. Each six-input LUT comprises two five-input lookup tables (LUT5s) that are used to form Booth encoding multiplier building blocks. The five inputs to each LUT5 are two bits from a multiplier and three Booth-encoded bits from a multiplicand. By assembling building blocks, multipliers of arbitrary size may be formed.Type: ApplicationFiled: February 27, 2020Publication date: June 18, 2020Inventors: Daniel Pugh, Raymond Nijssen
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Patent number: 10656915Abstract: In some example embodiments a logical block comprising twelve inputs and two six-input lookup tables (LUTs) is provided, wherein four of the twelve inputs are provided as inputs to both of the six-input lookup tables. This configuration supports efficient field programmable gate array (FPGA) implementation of multipliers. Each six-input LUT comprises two five-input lookup tables (LUT5s) that are used to form Booth encoding multiplier building blocks. The five inputs to each LUT5 are two bits from a multiplier and three Booth-encoded bits from a multiplicand. By assembling building blocks, multipliers of arbitrary size may be formed.Type: GrantFiled: September 18, 2018Date of Patent: May 19, 2020Assignee: Achronix Semiconductor CorporationInventors: Daniel Pugh, Raymond Nijssen
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Publication number: 20200019375Abstract: In some example embodiments a logical block comprising twelve inputs and two six-input lookup tables (LUTs) is provided, wherein four of the twelve inputs are provided as inputs to both of the six-input lookup tables. This configuration supports efficient field programmable gate array (FPGA) implementation of multipliers. Each six-input LUT comprises two five-input lookup tables (LUT5s) that are used to form Booth encoding multiplier building blocks. The five inputs to each LUT5 are two bits from a multiplier and three Booth-encoded bits from a multiplicand. By assembling building blocks, multipliers of arbitrary size may be formed.Type: ApplicationFiled: September 18, 2018Publication date: January 16, 2020Inventors: Daniel Pugh, Raymond Nijssen
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Patent number: 8661378Abstract: Methods, systems, and circuits that implement timing analyses of an asynchronous system are described. A method may include converting a synchronous circuit design into an asynchronous representation, wherein a critical path may be identified. The critical path may be converted to a corresponding path in the synchronous circuit design. Additional methods, systems, and circuits are disclosed.Type: GrantFiled: September 30, 2009Date of Patent: February 25, 2014Assignee: Achronix Semiconductor CorporationInventors: Rajit Manohar, Gael Paul, Raymond Nijssen, Marcel Van der Goot, Clinton W. Kelly, Virantha Ekanayake
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Patent number: 8593176Abstract: Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.Type: GrantFiled: January 13, 2012Date of Patent: November 26, 2013Assignee: Achronix Semiconductor CorporationInventors: Raymond Nijssen, Kamal Chaudhary, Rajit Manohar, Christopher LaFrieda, Clinton W. Kelly, Virantha Ekanayake
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Patent number: 8301933Abstract: Methods, systems, and circuits for implementing multi-clock designs in asynchronous logic circuits are described. A method may include associating one or more data tokens with a clock domain of a multi-clock domain netlist. A durational relationship between a clock period associated with the clock domain and one or more other clock domains of the multi-clock domain netlist may be determined. Data tokens used in other clock domains may be transformed based on the determined relationship.Type: GrantFiled: September 14, 2009Date of Patent: October 30, 2012Assignee: Achronix Semiconductor CorporationInventors: Rajit Manohar, Clinton W. Kelly, Virantha Ekanayake, Gael Paul, Raymond Nijssen, Marcel Van der Goot