Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may determine whether the IC temperature is less than a threshold value. The apparatus may initiate a joule heating procedure using a joule heating element of the IC upon determining that the temperature is less than the threshold value. The apparatus may delay an initiation of the one or more processors of the IC until the IC temperature meets the threshold value.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may determine whether the IC temperature is less than a threshold value. The apparatus may initiate a joule heating procedure using a joule heating element of the IC upon determining that the temperature is less than the threshold value. The apparatus may delay an initiation of the one or more processors of the IC until the IC temperature meets the threshold value.

Abstract: An integrated circuit includes a phase-locked-loop with fast clock synchronization recovery. A phase frequency detector is configured to receive a system clock signal and a feedback clock signal and to generate a comparison signal. A clock generator is configured to general a first clock signal based on the comparison signal, and an internal clock signal. A controller coupled to the clock generator and configured to deliver a mesh clock signal to a global clock mesh. A synchronizer coupled to the control logic and configured to generate a feedback clock signal to the phase frequency detector. The mesh clock signal is provided from the global clock mesh to the synchronizer. Advantages of the invention include the ability to operate the integrated circuit in a sleep state with a slow clock rate and then quickly recover to an operational clock rate.

Abstract: An integrated circuit includes a phase-locked-loop with fast clock synchronization recovery. A phase frequency detector is configured to receive a system clock signal and a feedback clock signal and to generate a comparison signal. A clock generator is configured to general a first clock signal based on the comparison signal, and an internal clock signal. A controller coupled to the clock generator and configured to deliver a mesh clock signal to a global clock mesh. A synchronizer coupled to the control logic and configured to generate a feedback clock signal to the phase frequency detector. The mesh clock signal is provided from the global clock mesh to the synchronizer. Advantages of the invention include the ability to operate the integrated circuit in a sleep state with a slow clock rate and then quickly recover to an operational clock rate.

Abstract: A flat panel display includes a plurality of pixel cells arranged in a rectangular matrix of columns and rows. Each pixel cell includes a pixel electrode, a primary storage element, and a switch for selectively coupling the pixel electrode with the primary storage element and a storage element of another pixel cell in an adjacent row or column. Columns and/or rows of redundant storage elements are provided, such that the switches of pixel cells in the last row or column of the display selectively couple the pixel electrode with a primary storage element and a redundant storage element.

Abstract: A display driver circuit includes a word line sequencer for providing a series of row addresses, and a row decoder for decoding each of the row addresses and asserting write signals on corresponding ones of a plurality of output terminals. An optional data path sequencer provides a series of path addresses which are used by an optional data router to route data to particular sub-rows of a display. Additionally, an optional sub-row sequencer provides a series of sub-row addresses to an optional sub-row decoder, which decodes each of the sub-row addresses and asserts write signals on corresponding ones of a second plurality of output terminals.

Abstract: A display driver circuit for reducing system interface band width requirements and peak current requirements includes a select line sequencer, for providing a series of select line addresses on an address terminal set, and a select line decoder coupled to the address terminal set, for decoding each of the select line addresses and asserting an update signal on a corresponding one of a plurality of output terminals. Optionally, the select line sequencer generates a series of select sub-line addresses, and the select line decoder is a select sub-line decoder. An optional select address register receives initial select addresses from a system and provides the initial select addresses to the select line sequencer. An alternate display driver circuit including a select line sequencer and a select sub-line sequencer is also described.

Abstract: A display driver circuit for reducing system interface band width requirements and peak current requirements includes a select line sequencer, for providing a series of select line addresses on an address terminal set, and a select line decoder coupled to the address terminal set, for decoding each of the select line addresses and asserting an update signal on a corresponding one of a plurality of output terminals. Optionally, the select line sequencer generates a series of select sub-line addresses, and the select line decoder is a select sub-line decoder. An optional select address register receives initial select addresses from a system and provides the initial select addresses to the select line sequencer. An alternate display driver circuit including a select line sequencer and a select sub-line sequencer is also described.

Abstract: A display driver circuit and method for receiving a display data stream, modifying the display data stream to enhance gray scale performance, and outputting the modified display data stream. The display driver includes a forced state generator for adding at least one forced state to the display data stream to create the modified display data stream. The forced state generator includes a multiplexer and a forced state controller. The multiplexer includes a data input terminal for receiving the display data stream, a first forced state input terminal for receiving first forced state data, a second forced state input terminal for receiving second forced state data, a data output terminal for outputting the modified display data stream, and a pair of control input terminals. The forced state controller includes a pair of control output terminals coupled the control input terminals of the multiplexer.

Abstract: A dual-port memory having an on-chip color register for storage of input data for use in multiple write cycles is disclosed. The color register is written to during a special cycle, which is enabled by a special function pin in conjunction with the write enable and transfer enable function pins, each of which have their logic state latched in during the row address strobe signal. A second type of special cycle causes a multiplexer to select the contents of the color register, rather than the latched data state of the data input terminals, for the data to be written to the selected memory cells. The use of the color register may be used in conjunction with a mask register, where the writing of certain input/outputs is inhibited. In addition, a block write feature may be incorporated with the color register so that, in another type of special cycle, multiple columns per input/output can be simultaneously written with the contents of the color register.

Abstract: A dual-port memory having an on-chip color register for storage of input data for use in multiple write cycles is disclosed. The color register is written to during a special cycle, which is enabled by a special function pin in conjunction with the write enable and transfer enable function pins, each of which have their logic state latched in during the row address strobe signal. A second type of special cycle causes a multiplexer to select the contents of the color register, rather than the latched data state of the data input terminals, for the data to be written to the selected memory cells. The use of the color register may be used in conjunction with a mask register, where the writing of certain input/outputs is inhibited. In addition, a block write feature may be incorporated with the color register so that, in another type of special cycle, multiple columns per input/output can be simultaneously written with the contents of the color register.

Abstract: A read/write memory for use with a central processing unit is disclosed, which has the capability of writing the same data state to multiple memory cells in a selected row in a single cycle. The invention is incorporated into the memory by a capacitor which is selectively connected to one of the bit lines received by each sense amplifier to override the sensing operation, thereby setting the polarity of the sensed differential voltage to a predetermined state. The restoring operation of the sense amplifier restores the sensed data state into the selected memory cell, completing the write. In response to a control signal generated in the read/write memory, the capacitor is connectable to multiple bit lines, for efficiency of design. Each capacitor has sufficient capacitance to fully discharge a stored "1" value plus the dummy capacitor charge, for each of the bit lines to which it will be connected.

Abstract: A read/write memory is disclosed, which has the capability of writing the same data state to multiple memory cells in a selected row in a single cycle. The invention is incorporated into the memory by a capacitor which is selectively connected to one of the bit lines received by each sense amplifier to override the sensing operation, thereby setting the polarity of the sensed differential voltage to a predetermined state. The restoring operation of the sense amplifier restores the sensed data state into the selected memory cell, completing the write. The capacitor may be connectable to multiple bit lines, for efficiency of design. Each capacitor has sufficient capacitance to fully discharge a stored "1" value plus the dummy capacitor charge, for each of the bit lines to which it will be connected. Logic is incorporated into the memory to receive the data state to be written, and to receive the least significant bit of the row address.

Abstract: In a video-type computer system and the like, an improved memory circuit is provided for adapting the system to CRT screens having different resolutions. The memory circuit includes a bit-mapped RAM unit or chip having sufficient cells to accommodate any CRT screen sought to be used, and also a serial shift register having taps at a plurality of different locations corresponding to different columns of cells in the RAM unit. When the RAM unit is in serial mode, a row of data is transferred into the serial shift register. Then the column address applied to the RAM unit is used to instruct and actuate a suitable decoder circuit to select the tap appropriate to unload the portion of the serial shift register containing the data bits of interest.

Abstract: In a video computer system having a dual-port bit-mapped RAM unit incorporating a shift register, provision is made for coupling data between column lines and the shift register, and for simultaneously preventing any column line from being coupled with the random data output terminal of the RAM unit. Accordingly, this prevents two or more different data bits from appearing simultaneously from the RAM unit and causing confusion as to which is the valid signal and which is a spurious signal.

Abstract: A dual-port memory having an on-chip color register for storage of input data for use in multiple write cycles is disclosed. The color register is written to during a special cycle, which is enabled by a special function pin in conjunction with the write enable and transfer enable function pins, each of which have their logic state latched in during the row address strobe signal. A second type of special cycle causes a multiplexer to select the contents of the color register, rather than the latched data state of the data input terminals, for the data to be written to the selected memory cells. The use of the color register may be used in conjunction with a mask register, where the writing of certain input/outputs is inhibited. In addition, a block write feature may be incorporated with the color register so that, in another type of special cycle, multiple columns per input/output can be simultaneously written with the contents of the color register.

Abstract: In a video-type computer system and the like, an improved memory circuit is provided for adapting the system to CRT screens having different resolutions. The memory circuit includes a bit-mapped RAM unit or chip having sufficient cells to accommodate any CRT screen sought to be used, and also a serial shift register having taps at a plurality of different locations corresponding to different columns of cells in the RAM unit. When the RAM unit is in serial mode, a row of data is transferred into the serial shift register. Then the column address applied to the RAM unit is used to instruct and actuate a suitable decoder circuit to select the tap appropriate to unload the portion of the serial shift register containing the data bits of interest.

Abstract: A dual-port memory which features a pipelined serial port is disclosed. The serial side of the dual-port memory contains a ripple counter which is broken between predetermined stages. The contents of the stages above the break are decoded to select a group of bits of the serial register for output, and the contents latched in a latch. In serial output, the contents of the stages below the break are decoded, so that responsive to the stages below the break reaching a certain value, the stages above the break are incremented and the incremented value decoded. Pass transistors between the register and the latch are turned off during such time as the incremented value is being decoded, so that the new value will not disturb the output. The latched output is selectively presented by a multiplexer which selects the latch bits responsive to the value of the stages below the break. Upon the value of the stages reaching its minimum value (i.e.

Abstract: A dual-port memory having an on-chip color register for storage of input data for use in multiple write cycles is disclosed. The color register is written to during a special cycle, which is enabled by a special function pin in conjunction with the write enable and transfer enable function pins, each of which have their logic state latched in during the row address strobe signal. A second type of special cycle causes a multiplexer to select the contents of the color register, rather than the latched data state of the data input terminals, for the data to be written to the selected memory cells. The use of the color register may be used in conjunction with a mask register, where the writing of certain input/outputs in inhibited. In addition, a block write feature may be incorporated with the color register so that, in another type of special cycle, multiple columns per input/output can be simulaneously written with the contents of the color register.

Abstract: In video computer system having a dual-port bit-mapped RAM unit incorporating a shift register, provision is made for coupling data between column lines and the shift register, and for simultaneously preventing any column line from being coupled with the random data output terminal of the RAM unit. Accordingly, this prevents two or more different data bits from appearing simultaneously from the RAM unit and causing confusion as to which is the valid signal and which is a spurious signal.