Patents by Inventor Raymond T. Lee

Raymond T. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7026691
    Abstract: A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.
    Type: Grant
    Filed: April 25, 2001
    Date of Patent: April 11, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Craig S. Sander, Rich K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Christoper A. Spence, Raymond T. Lee, John C. Holst, Stephen C. Horne
  • Patent number: 6479350
    Abstract: CMOS semiconductor devices comprising MOS transistors of different channel conductivity type are formed in or on a common semiconductor substrate using a minimum number of critical masks. Embodiments include forming conductive gate/insulator layer stacks on spaced-apart, different conductivity portions of the main surface of the substrate, forming etch-resistant inner sidewall spacers on side surfaces of the layer stacks, and forming easily etched, amorphous semiconductor disposable outer sidewall spacers on the inner sidewall spacers. The use of disposable outer sidewall spacers allows heavy and light source/drain implantations of opposite conductivity type to be performed for forming PMOS and NMOS transistors with the use of only two critical masks, thereby reducing production cost and duration, while increasing manufacturing throughput.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: November 12, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zicheng Gary Ling, Todd Lukanc, Raymond T. Lee
  • Patent number: 6287904
    Abstract: Metal oxide semiconductor devices are formed having gates with minimum endcap width and no source/drain leakage. A pair of source/drain regions is formed in a substrate, and a gate oxide is formed on the substrate. A layer of a conductive material, such as polysilicon, is formed on the gate oxide layer, masked and etched to form an extended-width gate having endcaps of a greater width than the endcap design rules. A second mask is formed to cover the extended-width gate up to the desired width of the endcaps (i.e., the design width) and to expose the portions of the extended-width gate beyond the endcap design width. The exposed portions of the extended-width gate are then etched, resulting in a completed gate having endcaps of the design width. Since the endcaps are initially formed to a greater width than the design width, any pullback that occurs during printing of the mask or etching of the gate does not cause the gate to be insufficiently wide to avoid source/drain leakage.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: September 11, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Raymond T. Lee, Zicheng Gary Ling
  • Patent number: 6287953
    Abstract: A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: September 11, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Craig S. Sander, Rich K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Christoper A. Spence, Raymond T. Lee, John C. Holst, Stephen C. Horne
  • Patent number: 6221706
    Abstract: MOS semiconductor devices of different conductivity types are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, and disposable aluminum sidewall spacers on the side surfaces of the gates. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the aluminum sidewall spacers on the unmasked gates are then removed, and lightly or moderately doped source/drain extension implants of the second impurity type are formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: April 24, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Todd Lukanc, Raymond T. Lee, Zicheng Gary Ling, Matthew S. Buynoski
  • Patent number: 6218224
    Abstract: Semiconductor devices of different conductivity types with optimized junction locations are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, sidewall spacers on side surfaces of the gates, and nitride disposable spacers on the sidewall spacers. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the nitride disposable spacers on the sidewall spacers on the unmasked gates removed, and lightly or moderately doped source/drain extension implants of the second impurity type formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface.
    Type: Grant
    Filed: March 26, 1999
    Date of Patent: April 17, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Todd Lukanc, Raymond T. Lee, Zicheng Gary Ling
  • Patent number: 6214655
    Abstract: Semiconductor devices of different conductivity types are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, and disposable amorphous silicon spacers on the sidewalls of the gates. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the disposable spacers on the unmasked gates are then removed, and lightly or moderately doped source/drain extension implants of the second impurity type are formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface.
    Type: Grant
    Filed: March 26, 1999
    Date of Patent: April 10, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Raymond T. Lee, Zicheng Gary Ling
  • Patent number: 6191034
    Abstract: A method of forming minimal gaps or spaces in conductive lines pattern for increasing the density of integrated circuits by first forming an opening in an insulating layer overlying the conductive line by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening, and using the sidewalls as a mask to remove, preferably by etching, a portion of the conductive line pattern substantially equal in size to the reduced opening.
    Type: Grant
    Filed: April 5, 1999
    Date of Patent: February 20, 2001
    Assignee: Advanced Micro Devices
    Inventors: Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Christopher A. Spence, Raymond T. Lee, John C. Holst, Stephen C. Horne
  • Patent number: 6146954
    Abstract: A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal insulating space between polysilicon gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET. A portion of an insulating layer between the source and drain is removed prior to forming the gate. Preferably, an etch stop layer on the semiconductor substrate underlying the insulating layer is used in the method.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: November 14, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Craig S. Sander, Christopher A. Spence, Raymond T. Lee, John C. Holst, Stephen C. Horne
  • Patent number: 6114235
    Abstract: A multipurpose cap layer serves as a bottom anti-reflective coating (BARC) during the formation of a resist mask, a hardmask during subsequent etching processes, a hardened surface during subsequent deposition and planarization processes, and optionally as a diffusion barrier to mobile ions from subsequently deposited materials.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: September 5, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David K. Foote, Minh Van Ngo, Christopher F. Lyons, Fei Wang, Raymond T. Lee, William G. En, Susan H. Chen, Darin A. Chan
  • Patent number: 6103563
    Abstract: Semiconductor devices of different conductivity types are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, and disposable nitride spacers on the sidewalls of the gates. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the disposable spacers on the unmasked gates are then removed, and lightly or moderately doped source/drain extension implants of the second impurity type are formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: August 15, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Todd Lukanc, Raymond T. Lee, Zicheng Gary Ling
  • Patent number: 6051881
    Abstract: A method and the resulting device to permit the formation of minimal insulating space between polysilicon gates by forming an insulating layer over the polysilicon gates and protecting selected ones of the gates and the insulating layer with an etch barrier so that the opening for local interconnect metallization can be misaligned and the selected gates will be protected by its etch barrier and not be exposed to the opening. Further, local interconnect conductive material can pass over a gate or unrelated resistor without shorting the gate/resistor.
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: April 18, 2000
    Assignee: Advanced Micro Devices
    Inventors: Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Craig S. Sander, Christopher A. Spence, Raymond T. Lee, John C. Holst, Stephen C. Horne
  • Patent number: 6046088
    Abstract: A method of forming field isolation in a semiconductor substrate, such as shallow oxide trenches, for isolation of FET transistors, including complementary FETs such as CMOS, with selected sections of said trenches extending above the substrate and being coplanar with the upper surface of subsequently formed polysilicon gates. An etch protective layer is used during the formation and the filling of the trench openings so that the top of the trenches are coplanar with upper surface of the etch protective layer. Selected sections of the trenches are masked and protected prior to planarization of the non-masked trenches to the bottom edge of the etch protective layer. After deposition and planarization of the poly, the upper surface of a deposited polysilicon layer for forming polysilicon gates of FET transistors is coplanar and self-aligned with the upwardly extending selected sections of the field isolation trenches.
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: April 4, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Craig S. Sander, Christopher A. Spence, Raymond T. Lee, John C. Holst, Stephen C. Horne
  • Patent number: 5930659
    Abstract: A method of forming minimal gaps or spaces in a polysilicon conductive lines pattern for increasing the density of integrated circuits by converting an area of the size of the desired gap or space in the polysilicon to silicon oxide, followed by removing the silicon oxide. The preferred method is to selectively ion implant oxygen into the polysilicon and annealing to convert the oxygen implanted polysilicon to silicon oxide. As an alternative method, an opening in an insulating layer overlying the conductive line is first formed by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening and using the sidewalls as a mask to blanket implant oxygen through the reduced opening and into the exposed polysilicon conductive line. After annealing, the implanted polysilicon converted to silicon oxide and removed to form a gap or space in the polysilicon conductive line pattern substantially equal in size to the reduced opening.
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: July 27, 1999
    Assignee: Advanced MicroDevices, Inc.
    Inventors: Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Christopher A. Spence, Raymond T. Lee, John C. Holst, Stephen C. Horne
  • Patent number: 5879980
    Abstract: A static random access memory (SRAM) cell having increased cell capacitance at the storage nodes utilizes a capacitive structure disposed in a trench. The capacitive structure includes an oxide liner disposed underneath a polysilicon or tungsten plug. The polysilicon plugs are each isolated from the drains of lateral transistors associated with the SRAM cell. The capacitive structure is provided between first and second N-channel pull down transistors associated with the SRAM cell. The polysilicon plug can be provided during the formation of local interconnects for the cell. The polysilicon material or plug can be coupled to the semiconductor substrate.
    Type: Grant
    Filed: March 24, 1997
    Date of Patent: March 9, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Asim A. Selcuk, Raymond T. Lee
  • Patent number: 5844836
    Abstract: A static random access memory (SRAM) cell having increased cell capacitance at the storage nodes utilizes a capacitive structure. The capacitive structure includes a dielectric material between polysilicon conductive lines and tungsten local interconnects. The polysilicon plates are each connected to drains of lateral transistors associated with the SRAM cell. A dielectric material such as silicon dioxide may be deposited between the local interconnect and polysilicon conductive lines. The capacitor structures are provided between first and second N-channel pull down transistors associated with the SRAM cell.
    Type: Grant
    Filed: March 24, 1997
    Date of Patent: December 1, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nicholas John Kepler, Asim A. Selcuk, Richard K. Klein, Craig S. Sander, John C. Holst, Christopher A. Spence, Raymond T. Lee, Stephen C. Horne
  • Patent number: 5796651
    Abstract: A memory device uses a reduced word line voltage during READ operations. The memory device includes a memory cell and a pass transistor for accessing the cell. The cell includes a storage node coupled to a pull-down transistor having substantially the same conductivity as the pass transistor. A drive circuit generates a reduced word line voltage to activate the pass transistor during a READ operation. The reduced word line voltage has a magnitude less than the magnitude of the bias voltage used to activate the pull-down transistor.
    Type: Grant
    Filed: May 19, 1997
    Date of Patent: August 18, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stephen C. Horne, Richard K. Klein, Asim A. Selcuk, Nicholas John Kepler, Christopher A. Spence, Raymond T. Lee, John C. Holst
  • Patent number: 5674781
    Abstract: The present invention is directed to a technology that simplifies the process of fabricating multilayer interconnects and reduces capacitance in integrated circuits employing multilayer interconnects. The novel landing pad technology of the present invention simplifies the current process steps involved in the formation of multilayer interconnects. The same contact/via etch, the same PVD TiN deposition, etc., can be modularized and repeated to build up multilayer metalization. The process of the present invention for forming multilayer interconnects involves the formation of Ti/TiN stack interconnect structures that can be used as local interconnects and contact landing pads on the same level. The contact landing pads facilitate the use of a borderless contact approach which enables a reduction in the size of the source-drain area. As the source-drain area is reduced, junction capacitance decreases, and packing density can be increased.
    Type: Grant
    Filed: February 28, 1996
    Date of Patent: October 7, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard J. Huang, Robin W. Cheung, Rajat Rakkhit, Raymond T. Lee
  • Patent number: 5654589
    Abstract: The present invention is directed to a technology that simplifies the process of fabricating multilayer interconnects and reduces capacitance in integrated circuits employing multilayer interconnects. The novel landing pad technology of the present invention simplifies the current process steps involved in the formation of multilayer interconnects. The same contact/via etch, the same PVD TiN deposition, etc., can be modularized and repeated to build up multilayer metalization. The process of the present invention for forming multilayer interconnects involves the formation of Ti/TiN stack interconnect structures that can be used as local interconnects and contact landing pads on the same level. The contact landing pads facilitate the use of a borderless contact approach which enables a reduction in the size of the source-drain area. As the source-drain area is reduced, junction capacitance decreases, and packing density can be increased.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: August 5, 1997
    Assignee: Advanced Micro Devices, Incorporated
    Inventors: Richard J. Huang, Robin W. Cheung, Rajat Rakkhit, Raymond T. Lee
  • Patent number: 5627110
    Abstract: A method of fabricating semiconductor devices which eliminates the need to use additional window mask process to expose topographical marks, such as alignment targets, on a wafer when chemical-mechanical polish planarization technique are used to substantially planarize the surface of the wafer prior to metal deposition.
    Type: Grant
    Filed: October 24, 1994
    Date of Patent: May 6, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Raymond T. Lee, Richard K. Klein