Abstract: A method, apparatus and system. The apparatus includes one or more processors to: determine that a memory operation including one of a write operation or a read operation is to be implemented on a memory cell of a memory array, the memory operation having a duration equal to a latency window and being based on a voltage change across the memory cell equal to a target memory window; and in response to a determination that the memory operation is to be implemented, cause, during the latency window, an application to the memory cell of a current pulse amplitude profile progressively decreasing between and including at least four current pulse amplitudes.

Abstract: A memory device comprising a plurality of memory cells, a memory cell of the plurality of memory cells comprising a phase change material (PM) region and a select device (SD) region in series with the PM region; a first address line and a second address line coupled to the memory cell; and memory controller circuitry to interface with the first address line and the second address line, the memory controller circuitry to encode a state in the memory cell by applying, through the first address line and second address line, a current spike and a programming pulse to the memory cell to cause the PM region to be placed into an amorphous state and the SD region of the memory cell to be placed into a high threshold voltage state.

Abstract: In one embodiment, a state is reach from a memory cell comprising a phase change material (PM) region and a select device (SD) region by: ramping a voltage applied to a first address line of an address line pair corresponding to the memory cell until the first address line voltage is stabilized at a predetermined voltage, ramping a voltage applied to a second address line of the address line pair corresponding to the memory cell, detecting a snap in the memory cell while ramping the voltage applied to the second address line, and determining a state of the memory cell based on a differential voltage between the first and second address lines when the memory cell snap occurred.

Abstract: In one embodiment, a state is encoded into a memory cell comprising a phase change material (PM) region and a select device (SD) region by: applying a first current in the memory cell over a first time period, wherein the first current applied over the first time period causes the PM region of the memory cell to be placed into an amorphous state and the SD region of the memory cell to be placed into an amorphous state; and applying a second current in the memory cell over a second time period after the first time period, wherein the second current applied over the third time period causes the SD region of the memory cell to be placed into a crystalline state and the PM region of the memory cell to remain in the amorphous state.

Abstract: Augmented reality features are selected for presentation to a display of an electronic eyewear device by using a camera of the electronic eyewear device to capture a scan image and processing the scan image to extract contextual signals. Simultaneously, voice data from the user is captured by a microphone of the electronic eyewear device and voice-to-text conversion of the captured voice data is performed to identify keywords in the voice data. The extracted contextual signals and the identified keywords are then used to select at least one augmented reality feature that matches the extracted contextual signals and the identified keywords, and the selected augmented reality feature is presented to the display for user selection. The contextual information thus refines the search results to provide the augmented reality feature best suited for the context of the scan image captured by the electronic eyewear device.

Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods that minimize energy expenditure and wear while providing greatly improved error rate with respect to marginal bits are disclosed and described.

Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods that minimize energy expenditure and wear while providing greatly improved error rate with respect to marginal bits are disclosed and described.

Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods of programming the nonvolatile memory including sensing of a snapback current using a set demarcation voltage for set bit mapped cells and a reset demarcation voltage for reset bit mapped cells before selective writes.

Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods of programming the nonvolatile memory including dual demarcation voltage sensing before writes.

Abstract: A charge pump circuit includes a voltage controlled oscillator. The voltage controlled oscillator operates at a lower frequency during a warm-up mode, and operates at a higher frequency during a loading mode. The lower frequency operation during the warm-up mode reduces power supply current requirements.

Abstract: A charge pump circuit includes a voltage controlled oscillator. The voltage controlled oscillator operates at a lower frequency during a warm-up mode, and operates at a higher frequency during a loading mode. The lower frequency operation during the warm-up mode reduces power supply current requirements.

Abstract: One or more MOS devices may be used as a bias selecting circuit to pass a bias voltage from a bias generator to a level shifting circuit.

Abstract: In one embodiment, the present invention includes a method to supply a negative voltage to at least one deselected wordline of a memory array. Further, while the negative voltage is supplied to deselected wordlines, a positive voltage may be supplied to a selected wordline. The memory array may be a flash memory incorporating multi-level cell architecture, in one embodiment.

Abstract: A method of providing multiple voltage outputs includes receiving an input signal from a multifunctional pump. The method also includes sending a first output signal based on the input signal using a first switch and sending a second output signal based on the input signal using a second switch and a transistor.

Abstract: A method of providing multiple voltage outputs includes receiving an input signal from a multifunctional pump. The method also includes sending a first output signal based on the input signal using a first switch and sending a second output signal based on the input signal using a second switch and a transistor.

Abstract: An apparatus to provide a novel bi-voltage level switching. The apparatus includes a first level shifting buffer coupled to a voltage supply, an input, and a first transistor. The first transistor coupled to the voltage supply and an output. A second level shifting buffer coupled to the voltage supply, the input and second transistor. The second transistor coupled to the output and a voltage source.

Abstract: A circuit includes (i) an N-channel device having a gate, a source connected to low voltage, and a drain connected to a memory select gate, (ii) a P-channel device having a gate, a source, and a drain connected to the drain of the N-channel device, and (iii) a voltage supply connected to the source of the P-channel device, the voltage supply switching between a first high voltage and a first lower voltage. A gate driver supplies, to the gates of the N-channel and P-channel devices, a second high voltage, a second low voltage, or an intermediary voltage between the second high voltage and second low voltage. The gate driver supplies the intermediary voltage when the voltage supply switches between the first high voltage and first lower voltage.