Abstract: A DMOS transistor integrates a trench Schottky diode into the body contact of the transistor where the body region surrounding the Schottky metal layer forms a guard ring for the Schottky diode.

Abstract: A DMOS transistor integrates a trench Schottky diode into the body contact of the transistor where the body region surrounding the Schottky metal layer forms a guard ring for the Schottky diode.

Abstract: A DMOS transistor integrates a trench Schottky diode into the body contact of the transistor where the body region surrounding the Schottky metal layer forms a guard ring for the Schottky diode.

Abstract: A DMOS transistor integrates a trench Schottky diode into the body contact of the transistor where the body region surrounding the Schottky metal layer forms a guard ring for the Schottky diode.

Abstract: A planar vertical DMOS transistor uses a conductive spacer structure formed on the sides of a dielectric structure as the gate of the transistor. The planar vertical DMOS transistor with a conductive spacer gate structure reduces the parasitic gate-to-bulk or gate-to-drain overlap capacitance by eliminating the conductive gate material that is formed above the bulk of the semiconductor layer. Meanwhile, the desired distance between the body regions formed on opposing sides of the conductive spacer gate structure is maintained.

Abstract: A planar vertical DMOS transistor includes a dielectric separation structure formed under the conductive gate and over the bulk of the semiconductor layer outside of the channel region of the transistor. The planar vertical DMOS transistor with a conductive gate formed over the dielectric structure reduces the parasitic gate-to-bulk or gate-to-drain overlap capacitance by increasing the separation between the conductive gate and the bulk of the semiconductor layer. Meanwhile, the desired distance between the body regions formed on opposing sides of the conductive gate is maintained.

Abstract: A planar vertical DMOS transistor uses a conductive spacer structure formed on the sides of a dielectric structure as the gate of the transistor. The planar vertical DMOS transistor with a conductive spacer gate structure reduces the parasitic gate-to-bulk or gate-to-drain overlap capacitance by eliminating the conductive gate material that is formed above the bulk of the semiconductor layer. Meanwhile, the desired distance between the body regions formed on opposing sides of the conductive spacer gate structure is maintained.

Abstract: A planar vertical DMOS transistor includes a dielectric separation structure formed under the conductive gate and over the bulk of the semiconductor layer outside of the channel region of the transistor. The planar vertical DMOS transistor with a conductive gate formed over the dielectric structure reduces the parasitic gate-to-bulk or gate-to-drain overlap capacitance by increasing the separation between the conductive gate and the bulk of the semiconductor layer. Meanwhile, the desired distance between the body regions formed on opposing sides of the conductive gate is maintained.

Abstract: A master transceiver automatically lowers its transmit power level at intervals until a slave transceiver no longer accurately receives the transmitted data. When the master detects an inaccurate transfer of data, the master incrementally increases the transmit power level until it is determined that there has been an accurate transfer of data. At that time, the master transmits an acknowledge signal to the slave. Since the automatic power adjust routine is performed using the transmitted data from the master and the error control information transmitted by the slave, there is little or no overhead used by the power adjust routine. Simple control circuitry can be used to carry out the functions.

Abstract: In a method to form a DMOS or bipolar transistor, two epitaxial silicon layers are grown over a silicon substrate instead of the typical one low-resistivity epitaxial layer. The bottom epitaxial layer has a relatively high resistivity of, for example 10 ohms-cm, while the upper epitaxial layer, acting as a drift region, may have a conventional low resistivity such as 3 ohms-cm. The bottom epi layer, being less doped than the upper epi layer, causes a wider and deeper depletion region to occur for a given drain or collector voltage, as compared to a depletion region where the entire epitaxial layer is formed of the upper epitaxial layer composition. Therefore, the parasitic capacitor's depletion region will be wider and deeper when employing the bottom epitaxial layer. The wider and deeper depletion region in the lower epitaxial layer lowers the overall parasitic capacitance value. This improves the switching speed of the transistor.

Abstract: A PFM-type voltage regulator circuit converts an unregulated input voltage into a regulated output voltage using a first transistor controlled by a pulse control circuit and a second transistor controlled by a linear regulator circuit. The linear regulator circuit controls the second transistor when the regulated output voltage falls to a predetermined minimum target voltage level, thereby maintaining the regulated output voltage at the minimum target voltage level. The pulse control circuit detects the current passing through the second transistor, and in response generates a pulse signal having a predetermined duration that fully turns on the first transistor. The voltage through the first transistor is converted to an increasing inductor current that refreshes the regulated output voltage to a maximum target voltage level. When the pulse signal ends, the regulated output voltage again begins to fall toward the predetermined minimum target voltage level, and the cycle is repeated.

Abstract: A master transceiver automatically lowers its transmit power level at intervals until a slave transceiver no longer accurately receives the transmitted data. When the master detects an inaccurate transfer of data, the master incrementally increases the transmit power level until it is determined that there has been an accurate transfer of data. At that time, the master transmits an acknowledge signal to the slave. Since the automatic power adjust routine is performed using the transmitted data from the master and the error control information transmitted by the slave, there is little or no overhead used by the power adjust routine. Simple control circuitry can be used to carry out the functions.

Abstract: A single chip hybrid regulator is disclosed having a first stage being a switching regulator and a second stage being a linear regulator. The switching regulator uses a filter circuit including an inductor and a capacitor. To make the hybrid regulator very small, the inductor value is selected so that the inductor saturates at a current level well below the maximum load current for the regulator. At low load currents, the small inductor does not saturate, and the regulated voltage applied to the input of the linear regulator presents only a small differential voltage across the series transistor of the linear regulator, resulting in very little power being wasted by the series transistor. At higher currents, the small inductor begins to saturate or fully saturates; however, the increased ripple is smoothed by the linear regulator.

Abstract: A voltage regulator is disclosed having a PWM portion and an LDO portion on a single chip. The PWM portion switches a large MOS transistor (or synchronous MOS transistors) at a high frequency to supply medium and high currents (e.g., 600 mA) to a load. During a standby mode, the regulator switches to an LDO mode and disables the PWM portion. The LDO mode controls a very small MOS series transistor to supply the standby mode current. Since the gate of the series MOS transistor is small, only a small variation in gate charge is needed to adequately control the conductance of the series transistor during the standby mode. Therefore, much less control current is used by the LDO than if the LDO used a series transistor of the same size as the switching transistor.

Abstract: A single chip hybrid regulator is disclosed having a first stage being a switching regulator and a second stage being a linear regulator. The switching regulator uses a filter circuit including an inductor and a capacitor. To make the hybrid regulator very small, the inductor value is selected so that the inductor saturates at a current level well below the maximum load current for the regulator. At low load currents, the small inductor does not saturate, and the regulated voltage applied to the input of the linear regulator presents only a small differential voltage across the series transistor of the linear regulator, resulting in very little power being wasted by the series transistor. At higher currents, the small inductor begins to saturate or fully saturates; however, the increased ripple is smoothed by the linear regulator.

Abstract: A single chip hybrid regulator is disclosed having a first stage being a switching regulator and a second stage being a linear regulator. The switching regulator uses a filter circuit including an inductor and a capacitor. To make the hybrid regulator very small, the inductor value is selected so that the inductor saturates at a current level well below the maximum load current for the regulator. At low load currents, the small inductor does not saturate, and the regulated voltage applied to the input of the linear regulator presents only a small differential voltage across the series transistor of the linear regulator, resulting in very little power being wasted by the series transistor. At higher currents, the small inductor begins to saturate or fully saturates; however, the increased ripple is smoothed by the linear regulator.