Patents by Inventor Rebecca Mih
Rebecca Mih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6727589Abstract: A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.Type: GrantFiled: November 30, 2000Date of Patent: April 27, 2004Assignee: International Business Machines CorporationInventors: Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava
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Patent number: 6479884Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.Type: GrantFiled: June 29, 2001Date of Patent: November 12, 2002Assignee: International Business Machines CorporationInventors: Robert Cook, Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava
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Patent number: 6429067Abstract: A method for fabricating a dual gate structure, comprising providing a semiconductor substrate having a first device area and a second device area covered by a gate oxide layer and a polysilicon layer, forming a first hard mask over the polysilicon layer, said first hard mask being a material that is resistant to a first etching, but susceptible to a second etching forming a second hard mask over the first hard mask and the polysilicon layer, said second hard mask being a material that is resistant to a second etching, but susceptible to a first etching, patterning and etching said second hard mask with a first etch to form a gate pattern on a first device area, and patterning and etching said first hard mask with a second etch to transfer gate patterns on the first and second device areas.Type: GrantFiled: January 17, 2001Date of Patent: August 6, 2002Assignee: International Business Machines CorporationInventors: Joyce C. Liu, James C. Brighten, Jeffrey J. Brown, John Golz, George A. Kaplita, Rebecca Mih, Senthil Srinivasan, Jin Jwang Wu, Teresa J. Wu, Chienfan Yu
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Publication number: 20020094637Abstract: A method for fabricating a dual gate structure, comprising providing a semiconductor substrate having a first device area and a second device area covered by a gate oxide layer and a polysilicon layer, forming a first hard mask over the polysilicon layer, said first hard mask being a material that is resistant to a first etching, but susceptible to a second etching forming a second hard mask over the first hard mask and the polysilicon layer, said second hard mask being a material that is resistant to a second etching, but susceptible to a first etching, patterning and etching said second hard mask with a first etch to form a gate pattern on a first device area, and patterning and etching said first hard mask with a second etch to transfer gate patterns on the first and second device areas.Type: ApplicationFiled: January 17, 2001Publication date: July 18, 2002Applicant: International Business Machines CorporationInventors: Joyce C. Liu, James C. Brighten, Jeffrey J. Brown, John Golz, George A. Kaplita, Rebecca Mih, Senthil Srinivasan, Jin Jwang Wu, Teresa J. Wu, Chienfan Yu
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Patent number: 6348736Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. A first protective layer is formed in situ on the dielectric material, such as by exposing the material to an oxygen-containing or flourine containing plasma. Also, by performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. The first protective layer and the surface protective covering can be formed by essentially identical processes.Type: GrantFiled: October 29, 1999Date of Patent: February 19, 2002Assignee: International Business Machines CorporationInventors: Vincent J. McGahay, John P. Hummel, Joyce Liu, Rebecca Mih, Kamalesh Srivastava, Robert Cook, Stephen E. Greco
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Patent number: 6329280Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.Type: GrantFiled: May 13, 1999Date of Patent: December 11, 2001Assignee: International Business Machines CorporationInventors: Robert Cook, Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava
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Publication number: 20010036739Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.Type: ApplicationFiled: June 29, 2001Publication date: November 1, 2001Inventors: Robert Cook, Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava
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Patent number: 6221780Abstract: A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.Type: GrantFiled: September 29, 1999Date of Patent: April 24, 2001Assignee: International Business Machines CorporationInventors: Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava
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Publication number: 20010000115Abstract: A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer nay be either a single damascene or a dual damascene layer.Type: ApplicationFiled: November 30, 2000Publication date: April 5, 2001Inventors: Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava