Patents by Inventor Reda R. Razouk
Reda R. Razouk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8822266Abstract: Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.Type: GrantFiled: January 25, 2011Date of Patent: September 2, 2014Assignee: National Semiconductor CorporationInventors: Peter Smeys, Peter Johnson, Peter Deane, Reda R. Razouk
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Patent number: 8686332Abstract: An optically-controlled shunt (OCS) circuit includes a switch and a light sampler. The light sampler is coupled to the switch and is configured to sample light at a photovoltaic (PV) cell corresponding to the OCS circuit and to turn on the switch when the sampled light comprises insufficient light for the PV cell. The light sampler may also be configured to turn off the switch when the sampled light comprises sufficient light for the PV cell. The light sampler may further be configured to partially turn on the switch when the sampled light comprises adequate light for the PV cell and to turn off the switch when the sampled light comprises full light for the PV cell. The switch could include a transistor, and the light sampler could include a photodiode.Type: GrantFiled: March 7, 2011Date of Patent: April 1, 2014Assignee: National Semiconductor CorporationInventors: Reda R. Razouk, Peter J. Hopper
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Publication number: 20120228480Abstract: An optically-controlled shunt (OCS) circuit includes a switch and a light sampler. The light sampler is coupled to the switch and is configured to sample light at a photovoltaic (PV) cell corresponding to the OCS circuit and to turn on the switch when the sampled light comprises insufficient light for the PV cell. The light sampler may also be configured to turn off the switch when the sampled light comprises sufficient light for the PV cell. The light sampler may further be configured to partially turn on the switch when the sampled light comprises adequate light for the PV cell and to turn off the switch when the sampled light comprises full light for the PV cell. The switch could include a transistor, and the light sampler could include a photodiode.Type: ApplicationFiled: March 7, 2011Publication date: September 13, 2012Applicant: NATIONAL SEMICONDUCTOR CORPORATIONInventors: Reda R. Razouk, Peter J. Hopper
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Publication number: 20110115071Abstract: Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.Type: ApplicationFiled: January 25, 2011Publication date: May 19, 2011Applicant: NATIONAL SEMICONDUCTOR CORPORATIONInventors: Peter Smeys, Peter Johnson, Peter Deane, Reda R. Razouk
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Patent number: 7902661Abstract: Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.Type: GrantFiled: December 21, 2009Date of Patent: March 8, 2011Assignee: National Semiconductor CorporationInventors: Peter Smeys, Peter Johnson, Peter Deane, Reda R. Razouk
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Publication number: 20100213603Abstract: Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.Type: ApplicationFiled: December 21, 2009Publication date: August 26, 2010Applicant: NATIONAL SEMICONDUCTOR CORPORATIONInventors: Peter SMEYS, Peter JOHNSON, Peter DEANE, Reda R. RAZOUK
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Patent number: 6548323Abstract: A process for preparing a light-sensitive integrated circuit (IC) for packaging that provides a reduced exposure of the light-sensitive IC to light. The process includes providing a semiconductor substrate (e.g., a silicon wafer) with a plurality of light-sensitive ICs formed in/on its upper surface. The lower surface is optionally coated with opaque material. Next, the semiconductor substrate is diced to form individual light-sensitive ICs, each of which has a semiconductor substrate lower surface and semiconductor substrate lateral edges. The semiconductor substrate lateral edges (and optionally backside) are then spray coated with an opaque material (e.g., opaque ink) to form an opaque layer covering the semiconductor substrate lateral edges. The opaque layer prevents light from entering the semiconductor substrate through the lateral edges and interfering with the operation of the light-sensitive IC.Type: GrantFiled: July 31, 2000Date of Patent: April 15, 2003Assignee: National Semiconductor CorporationInventors: Jeffrey R. Perry, Michael E. Thomas, Robert A. Sabsowitz, Reda R. Razouk, Aaron G. Simmons
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Patent number: 5911109Abstract: A trench which has walls intersecting a surface of a semiconductor substrate and an oxidation/diffusion barrier layer lining the walls is disclosed. The oxidation/diffusion barrier extends over the edges of the trench to prevent, for example, stress defects in the trench corners and vertical bird's beak formation within the trench. A filler material such as polysilicon is deposited within the trench followed by the deposition of a planarizing layer over the trench. After heat is applied, the planarizing layer flows to form a planarized layer over the trench. Using high pressure and phosphosilicate glass for the planarizing layer, the planarizing layer flows appropriately at low temperatures for short times.Type: GrantFiled: February 13, 1997Date of Patent: June 8, 1999Assignee: National Semiconductor CorporationInventors: Reda R. Razouk, Kulwant S. Egan, Wipawan Yindeepol, Waclaw C. Koscielniak
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Patent number: 5581110Abstract: A trench which has walls intersecting a surface of a semiconductor substrate and an oxidation/diffusion barrier layer lining the walls is disclosed. The oxidation/diffusion barrier extends over the edges of the trench to prevent, for example, stress defects in the trench corners and vertical bird's beak formation within the trench. A filler material such as polysilicon is deposited within the trench followed by the deposition of a planarizing layer over the trench. After heat is applied, the planarizing layer flows to form a planarized layer over the trench. Using high pressure and phosphosilicate glass for the planarizing layer, the planarizing layer flows appropriately at low temperatures for short times.Type: GrantFiled: August 17, 1995Date of Patent: December 3, 1996Assignee: National Semiconductor CorporationInventors: Reda R. Razouk, Kulwant S. Egan, Wipawan Yindeepol, Waclaw C. Koscielniak
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Patent number: 5179031Abstract: A method of making bipolar and MOS devices simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrystalline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution.Type: GrantFiled: July 19, 1990Date of Patent: January 12, 1993Assignee: National Semiconductor CorporationInventors: Michael P. Brassington, Reda R. Razouk, Monir H. El-Diwany, Prateep Tuntasood
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Patent number: 5124817Abstract: Bipolar and MOS devices are made simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrystalline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution.Type: GrantFiled: May 2, 1991Date of Patent: June 23, 1992Assignee: National Semiconductor CorporationInventors: Michael P. Brassington, Reda R. Razouk, Monir H. El-Diwany, Prateep Tuntasood
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Patent number: 5082796Abstract: A method of constructing a semiconductor structure wherein the polysilicon gate layer in a CMOS or BiCMOS structure incorporating LDD structures may be used for local interconnect. In one embodiment of the invention directed to a BiCMOS process, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide then is thermally grown on the silicon substrate. A thin layer of polysilicon is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing, and then both the thin polysilicon layer and the gate oxide layer are etched from the bipolar and MOS regions where the respective emitter and gates are to be formed and where buried contacts are to be made. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for defining the bipolar emitter, the MOS gates, and the local interconnects.Type: GrantFiled: July 24, 1990Date of Patent: January 21, 1992Assignee: National Semiconductor CorporationInventors: Monir H. El-Diwany, Michael P. Brassington, Reda R. Razouk
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Patent number: 5081518Abstract: A method of constructing a semiconductor structure wherein the polysilicon gate layer in a CMOS or BICMOS structure incorporating LDD structures may be used for local interconnect. In one embodiment of the invention directed to a BiCMOS process, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide then is thermally grown on the silicon substrate. A thin layer of polysilicon is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing, and then both the thin polysilicon layer and the gate oxide layer are etched from the bipolar and MOS regions where the respective emitter and gates are to be formed and where buried contacts are to be made. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for defining the bipolar emitter, the MOS gates, and the local interconencts.Type: GrantFiled: July 26, 1990Date of Patent: January 14, 1992Assignee: National Semiconductor CorporationInventors: Monir H. El-Diwany, Michael P. Brassington, Reda R. Razouk
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Patent number: 5001081Abstract: A method of making bipolar and MOS devices simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrystalline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution.Type: GrantFiled: October 6, 1989Date of Patent: March 19, 1991Assignee: National Semiconductor Corp.Inventors: Prateep Tuntasood, Michael P. Brassington, Reda R. Razouk, Monir H. El-Diwany