Patents by Inventor Reddy Raju
Reddy Raju has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11968309Abstract: Methods and systems for authenticating operations of an aircraft are disclosed. In at least one embodiment, the method may include: receiving, by an aircraft data gateway, a request for an operation of an aircraft from an operations portal; performing a first digital authentication of the request using first digital authentication information; performing a second digital authentication of the request using second digital authentication information, the second digital authentication information being distinct from the first digital authentication information; and executing the operation of the aircraft upon validating the first digital authentication and the second digital authentication.Type: GrantFiled: October 16, 2020Date of Patent: April 23, 2024Assignee: HONEYWELL INTERNATIONAL INC.Inventors: Vijayshankaran Iyer, Phani Ammi Raju Pothula, Kovalan Ramana, G V Bharath Kumar, Raveendra Reddy Mudimala, Paul Drake, Lawrence Marsala
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Patent number: 9036678Abstract: A fiber coupled semiconductor device and a method of manufacturing of such a device are disclosed. The method provides an improved stability of optical coupling during assembly of the device, whereby a higher optical power levels and higher overall efficiency of the fiber coupled device can be achieved. The improvement is achieved by attaching the optical fiber to a vertical mounting surface of a fiber mount. The platform holding the semiconductor chip and the optical fiber can be mounted onto a spacer mounted on a base. The spacer has an area smaller than the area of the platform, for mechanical decoupling of thermally induced deformation of the base from a deformation of the platform of the semiconductor device. Optionally, attaching the fiber mount to a submount of the semiconductor chip further improves thermal stability of the packaged device.Type: GrantFiled: July 27, 2010Date of Patent: May 19, 2015Assignee: JDS Uniphase CorporationInventors: Reddy Raju, Richard L. Duesterberg, Jay A. Skidmore, Prasad Yalamanchili, Xiangdong Qiu
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Patent number: 9008139Abstract: A high field of view, low height package and wafer-level packaging process are provided. The top surface of a first wafer has recesses defined by sidewalls, with a reflector, and a floor. The reflector is incident a horizontal light path form an edge-emitting diode on the floor, directing the light path vertically. A second optically diffusing wafer receives the vertically directed light. A vertical ring to surround each recess is wafer-level fabricated on one of the wafers. The vertical ring may have a high aspect ratio to increase light diffusion. The second wafer is connected above the first such that each vertical ring encloses its corresponding recess and such that the light vertically exits the optically diffusing media after spanning the height of the vertical ring. Diode electrical connections are provided for externally controlling the diode. Individual packages are separated by double-dicing the connected wafers between the recesses.Type: GrantFiled: June 28, 2013Date of Patent: April 14, 2015Assignee: JDS Uniphase CorporationInventors: Pezhman Monadgemi, Vincent V. Wong, Prasad Yalamanchili, Reddy Raju, Erik Paul Zucker, Jay A. Skidmore
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Publication number: 20150003482Abstract: A high field of view, low height package and wafer-level packaging process are provided. The top surface of a first wafer has recesses defined by sidewalls, with a reflector, and a floor. The reflector is incident a horizontal light path form an edge-emitting diode on the floor, directing the light path vertically. A second optically diffusing wafer receives the vertically directed light. A vertical ring to surround each recess is wafer-level fabricated on one of the wafers. The vertical ring may have a high aspect ratio to increase light diffusion. The second wafer is connected above the first such that each vertical ring encloses its corresponding recess and such that the light vertically exits the optically diffusing media after spanning the height of the vertical ring. Diode electrical connections are provided for externally controlling the diode. Individual packages are separated by double-dicing the connected wafers between the recesses.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Applicant: JDS Uniphase CorporationInventors: Pezhman MONADGEMI, Vincent V. WONG, Prasad YALAMANCHILI, Reddy RAJU, Erik Paul ZUCKER, Jay A. SKIDMORE
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Patent number: 8475056Abstract: A fiber coupled semiconductor device having an improved optical stability with respect to temperature variation is disclosed. The stability improvement is achieved by placing the platform holding the semiconductor chip and the optical fiber onto a spacer mounted on a base. The spacer has an area smaller than the area of the platform, for mechanical decoupling of thermally induced deformation of the base from a deformation of the platform of the semiconductor device. Attaching the optical fiber to a vertical mounting surface of a fiber mount, and additionally attaching the fiber mount to a submount of the semiconductor chip further improves thermal stability of the packaged device.Type: GrantFiled: July 26, 2010Date of Patent: July 2, 2013Assignee: JDS Uniphase CorporationInventors: Prasad Yalamanchili, Xiangdong Qiu, Reddy Raju, Jay A. Skidmore, Michael Au, Laura Zavala, Richard L. Duesterberg
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Patent number: 8215850Abstract: A molded ceramic or glass ferrule has at least one longitudinal passage, which enables an optical fiber feed through, sealed into a metal housing with glass solder. The metal material in the housing has a slightly higher coefficient of thermal expansion (CTE) than the ferrule material and the sealing glass so that hermetic seal is maintained by a compression stress applied to the ferrule and sealing glass by the housing at operating conditions. When the housing has to be fabricated from a low CTE material, e.g. metal or ceramic, a metal sleeve and stress relief bracket is used to apply the compression stress.Type: GrantFiled: December 29, 2009Date of Patent: July 10, 2012Inventors: Prasad Yalamanchili, Xiangdong Qiu, Reddy Raju, Jihua Du
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Publication number: 20110158594Abstract: A molded ceramic or glass ferrule has at least one longitudinal passage, which enables an optical fiber feed through, sealed into a metal housing with glass solder. The metal material in the housing has a slightly higher coefficient of thermal expansion (CTE) than the ferrule material and the sealing glass so that hermetic seal is maintained by a compression stress applied to the ferrule and sealing glass by the housing at operating conditions. When the housing has to be fabricated from a low CTE material, e.g. metal or ceramic, a metal sleeve and stress relief bracket is used to apply the compression stress.Type: ApplicationFiled: December 29, 2009Publication date: June 30, 2011Applicants: JDS Uniphase CorporationInventors: Prasad YALAMANCHILI, Xiangdong Qiu, Reddy Raju, Jihua Du
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Publication number: 20110026877Abstract: A fiber coupled semiconductor device having an improved optical stability with respect to temperature variation is disclosed. The stability improvement is achieved by placing the platform holding the semiconductor chip and the optical fiber onto a spacer mounted on a base. The spacer has an area smaller than the area of the platform, for mechanical decoupling of thermally induced deformation of the base from a deformation of the platform of the semiconductor device. Attaching the optical fiber to a vertical mounting surface of a fiber mount, and additionally attaching the fiber mount to a submount of the semiconductor chip further improves thermal stability of the packaged device.Type: ApplicationFiled: July 26, 2010Publication date: February 3, 2011Inventors: Prasad YALAMANCHILI, Xiangdong QIU, Reddy RAJU, Jay A. SKIDMORE, Michael AU, Laura ZAVALA, Richard L. DUESTERBERG
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Publication number: 20110026558Abstract: A fiber coupled semiconductor device and a method of manufacturing of such a device are disclosed. The method provides an improved stability of optical coupling during assembly of the device, whereby a higher optical power levels and higher overall efficiency of the fiber coupled device can be achieved. The improvement is achieved by attaching the optical fiber to a vertical mounting surface of a fiber mount. The platform holding the semiconductor chip and the optical fiber can be mounted onto a spacer mounted on a base. The spacer has an area smaller than the area of the platform, for mechanical decoupling of thermally induced deformation of the base from a deformation of the platform of the semiconductor device. Optionally, attaching the fiber mount to a submount of the semiconductor chip further improves thermal stability of the packaged device.Type: ApplicationFiled: July 27, 2010Publication date: February 3, 2011Applicant: JDS Uniphase CorporationInventors: Reddy RAJU, Richard L. Duesterberg, Jay A. Skidmore, Prasad Yalamanchili, Xiangdong Qiu
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Patent number: 6232157Abstract: The specification describes thin film transistor integrated circuits wherein the TFT devices are field effect transistors with inverted structures. The interconnect levels are produced prior to the formation of the transistors. This structure leads to added flexibility in processing. The inverted structure is a result of removing the constraints in traditional semiconductor field effect device manufacture that are imposed by the necessity of starting the device fabrication with the single crystal semiconductor active material. In the inverted structure the active material, preferably an organic semiconductor, is formed last in the fabrication sequence. In a preferred embodiment the inverted TFT devices are formed on a flexible printed circuit substrate.Type: GrantFiled: November 29, 1999Date of Patent: May 15, 2001Assignee: Agere Systems Inc.Inventors: Ananth Dodabalapur, Yen-Yi Lin, Venkataram Reddy Raju
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Patent number: 6197663Abstract: A process for fabricating an integrated circuit device is disclosed. The integrated circuit has a plurality of TFTs and an electrical interconnect structure. In the process, at least some constituents of the TFTs are formed on a first substrate. At least the interconnect structure is formed on a second substrate. The two substrates are laminated together to form the integrated circuit device having fully formed TFTs.Type: GrantFiled: December 7, 1999Date of Patent: March 6, 2001Assignee: Lucent Technologies Inc.Inventors: Edwin Arthur Chandross, Ananth Dodabalapur, Howard Edan Katz, Venkataram Reddy Raju
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Patent number: 6160645Abstract: A holographic medium uses a photosensitive polymer medium. The shelf life of the photosensitive polymer medium is improved by hermetically sealing the polymer between glass plates. The hermetic seal is designed so that high T.sub.g materials, or solder, can be used as the sealant without damage to the polymer already contained between the plates. The hermetic seal comprises metal foils attached to the plates with the edges thereof extending away from the plates in tab-like fashion. The foils are attached prior to filling the assembly with polymer. After filling, the outer edges of the foil tabs are the sealed with local heating away from the site of the polymer, or crimped using mechanical crimping.Type: GrantFiled: October 26, 1999Date of Patent: December 12, 2000Assignee: Lucent Technologies Inc.Inventors: Edwin Arthur Chandross, Venkataram Reddy Raju, Marcia Lea Schilling, Jeffrey Linn Bream
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Patent number: 6150668Abstract: A device in which one or more thin film transistors are monolithically integrated with a light emitting diode is disclosed. The thin film transistor has an organic semiconductor layer. The light emitting layer of the light emitting diode is also an organic material. The device is fabricated economically by integrating the fabrication of the thin film transistor and the light emitting diode on the substrate and by employing low cost fabrication techniques.Type: GrantFiled: September 8, 1999Date of Patent: November 21, 2000Assignee: Lucent Technologies Inc.Inventors: Zhenan Bao, Ananth Dodabalapur, Howard Edan Katz, Venkataram Reddy Raju, John A. Rogers
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Patent number: 6107117Abstract: A process for fabricating thin film transistors in which the active layer is an organic semiconducting material with a carrier mobility greater than 10.sup.-3 cm.sup.2 /Vs and a conductivity less than about 10.sup.-6 S/cm at 20.degree. C. is disclosed. The organic semiconducting material is a regioregular (3-alkylthiophene) polymer. The organic semiconducting films are formed by applying a solution of the regioregular polymer and a solvent over the substrate. The poly (3-alkylthiophene) films have a preferred orientation in which the thiophene chains has a planar stacking so the polymer backbone is generally parallel to the substrate surface.Type: GrantFiled: December 20, 1996Date of Patent: August 22, 2000Assignee: Lucent Technologies Inc.Inventors: Zhenan Bao, Ananth Dodabalapur, Yi Feng, Venkataram Reddy Raju
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Patent number: 6020219Abstract: A fragile device, such as an integrated circuit chip or a multichip assembly, is packaged by first dispensing a sol surrounding the sides of the device. The sol is laterally confined by means of a rim member typically made of a pre-molded plastic material. The amount of the sol dispensed is not sufficient to run over the top of the rim member. The sol is then heated to form a gel. If desired, a cover member can be put into place onto the top surface of the rim member, for the purpose of additional mechanical protection of the fragile device, for example.Type: GrantFiled: September 26, 1997Date of Patent: February 1, 2000Assignee: Lucent Technologies Inc.Inventors: Thomas Dixon Dudderar, Byung Joon Han, Venkataram Reddy Raju, George John Shevchuk
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Patent number: 5767447Abstract: The bottom and side surfaces of an electronic device, such as an integrated circuit chip or a multichip assembly, are surrounded by a soft gel medium. The gel medium is laterally confined by a rigid plastic rim that is epoxy-bonded in place along its perimeter. A plate, made of plastic or metal, can be attached to the top surface of the rim, in order to provide a cover for the package.Type: GrantFiled: December 5, 1995Date of Patent: June 16, 1998Assignee: Lucent Technologies Inc.Inventors: Thomas Dixon Dudderar, Byung Joon Han, Venkataram Reddy Raju, George John Shevchuk