Patents by Inventor REGAN STANLEY TSUI

REGAN STANLEY TSUI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9299710
    Abstract: A manufacturing method of capacitor lower electrode of the instant disclosure comprises the steps of: providing a semiconductor substrate; forming a sacrificial laminate on the semiconductor substrate; forming a plurality of capacitor trenches in the sacrificial laminate; forming a plurality of lower electrode structures in the capacitor trenches respectively; etching back the sacrificial laminate to a desired thickness to expose an upper portion of each of the lower electrode structures; forming a liner layer to conformally cover the sacrificial laminate and the upper portions of the lower electrode structures; patterning the liner layer to form an insulating spacer on the sidewalls of each of the upper portions, wherein two adjacent insulating spacers are configured to have a self-aligned opening positioned therebetween; and performing a wet-etching process to remove the sacrificial laminate through the self-aligned openings.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: March 29, 2016
    Assignee: Inotera Memories, Inc.
    Inventors: Regan Stanley Tsui, Tzung-Han Lee
  • Publication number: 20150214233
    Abstract: A manufacturing method of capacitor lower electrode of the instant disclosure comprises the steps of: providing a semiconductor substrate; forming a sacrificial laminate on the semiconductor substrate; forming a plurality of capacitor trenches in the sacrificial laminate; forming a plurality of lower electrode structures in the capacitor trenches respectively; etching back the sacrificial laminate to a desired thickness to expose an upper portion of each of the lower electrode structures; forming a liner layer to conformally cover the sacrificial laminate and the upper portions of the lower electrode structures; patterning the liner layer to form an insulating spacer on the sidewalls of each of the upper portions, wherein two adjacent insulating spacers are configured to have a self-aligned opening positioned therebetween; and performing a wet-etching process to remove the sacrificial laminate through the self-aligned openings.
    Type: Application
    Filed: April 14, 2014
    Publication date: July 30, 2015
    Applicant: INOTERA MEMORIES, INC.
    Inventors: REGAN STANLEY TSUI, TZUNG-HAN LEE
  • Patent number: 9053928
    Abstract: The present disclosure provides a wafer that can be used in coating films. The wafer includes a front surface, a back surface opposite to the front surface, and a plurality of trenches. The back surface further includes a central region and a surrounding region. The trenches are disposed on the back surface. The spacing between any two adjacent trenches in surrounding region is less than the spacing between any two adjacent trenches in the central region.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: June 9, 2015
    Assignee: Inotera Memories, Inc.
    Inventors: Eric Lahaug, Chia-Ming Yang, Regan Stanley Tsui
  • Publication number: 20140264774
    Abstract: The present disclosure provides a wafer that can be used in coating films. The wafer includes a front surface, a back surface opposite to the front surface, and a plurality of trenches. The back surface further includes a central region and a surrounding region. The trenches are disposed on the back surface. The spacing between any two adjacent trenches in surrounding region is less than the spacing between any two adjacent trenches in the central region.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 18, 2014
    Applicant: INOTERA MEMORIES, INC.
    Inventors: ERIC LAHAUG, CHIA-MING YANG, REGAN STANLEY TSUI