Abstract: A structural connector system for providing an electrical connection between electronic componentry is disclosed. The structural connector system includes a structural member, including an electrically insulating matrix, an electrically conducting path, a first end surface, a second end surface, and a first component engaging surface. The first component engaging surface includes a first mechanical coupler configured to mechanically couple a first electronic component or a first chassis component to the structural member and a first electrical coupler configured to electrically couple the first electronic component or the first chassis component to a first end of the electrically conducting path.

Abstract: A system and method for detecting and preventing cyberintrusion of a protected system incorporates neural networks having a training mode and a host-accessible (e.g., non-training) mode. When in training mode, the neural networks observe data exchanges with a protected system via interfaces (based on test inputs) and generate system templates corresponding to observed normal behaviors of the interfaces (including “gold standard” behavior indicative of optimal performance behaviors and/or minimal threat of cyberintrusion). When in host-accessible mode, the neural networks observe operating behaviors of the interfaces for each exchange via the interfaces and apply stored system templates to the system data to most closely approximate the optimal behavior set.

Abstract: A trusted image recognition system and method are disclosed. A target vehicle includes a target vehicle controller configured to generate a first cryptographic key having a first sequence of bits, and a mechanical key display device configured to display a mechanical representation of the first sequence of bits. A host vehicle includes an image sensor configured to capture an image of the mechanical representation of the first sequence of bits, and a host vehicle controller configured to: recognize the mechanical representation of the first sequence of bits in the image; retrieve the first sequence of bits of the first cryptographic key from the image; generate a second cryptographic key having a second sequence of bits; compare the first sequence of bits to the second sequence of bits; and, responsive to the first sequence of bits matching the second sequence of bits, identify the target vehicle as an authenticated target vehicle.

Abstract: A system is disclosed that includes an electronic package. The electronic package includes a package base couplable to a host substrate, and a package lid mechanically coupled to the package base that includes one or more transparent lid areas, configured to permit transmission of light. The electronic package further includes a thermal spreader bonded on a first side to a first side of the package lid. The thermal spreader includes one or more transparent spreader areas that are configured to allow transmission of light through the thermal spreader. The electronic package further includes one or more integrated circuits bonded to a second side of the thermal spreader that communicatively coupled to the host substrate. The electronic package further includes one or more optical paths that include at least one of the one or more transparent spreader areas configured adjacent to at least one of the transparent lid areas.

Abstract: An electronic assembly is disclosed. The electronic assembly includes a primary die, comprising a bulk layer, an integrated circuitry layer, a metal layer, a first redistribution layer, and a first attachment layer. The primary die further includes at least one aligned through-hole in the bulk layer and integrated circuitry layer. The electronic assembly further includes a secondary die physically coupled to the primary die via a second attachment layer. The electronic assembly further includes an interconnect header that includes plurality of interconnect filaments configured to electrically couple the first redistribution layer to one of the at least one metal layer via the at least one bulk layer through-hole and the at least one integrated circuitry through-hole. The interconnect header is generated by applying an electrically conductive filaments on a plurality of wafers, thinning the wafers, stacking and attaching the wafers into a wafer stack, and dicing the wafer stack.

Abstract: A first cryptographic communication system is disclosed. The first cryptographic communication system includes a common hardware module configured to receive local cryptographic signals and coalition cryptographic signals that includes a transmitter, a receiver, a common router, a trusted router, and a data loader. The first cryptographic communication system further includes a local cryptographic assembly and a coalition cryptographic assembly each including and end cryptographic unit communicatively coupled to the trusted router, a cross domain guard communicatively coupled to the end cryptographic unit and the trusted router, and a general purpose security module communicatively coupled to the cross domain guard. The first cryptographic communication system further includes a data recoding module communicatively coupled to the data loader that includes local and coalition data recording devices.

Abstract: A system and method for detecting and preventing cyberintrusion of a protected system incorporates neural networks having a training mode and a host-accessible (e.g., non-training) mode. When in training mode, the neural networks observe data exchanges with a protected system via interfaces (based on test inputs) and generate system templates corresponding to observed normal behaviors of the interfaces (including “gold standard” behavior indicative of optimal performance behaviors and/or minimal threat of cyberintrusion). When in host-accessible mode, the neural networks observe operating behaviors of the interfaces for each exchange via the interfaces and apply stored system templates to the system data to most closely approximate the optimal behavior set.

Abstract: A receiver device includes an acquisition engine and a reconfiguration engine. The acquisition engine uses a first circuit size. The acquisition engine is configured to receive a first signal including a plurality of first satellite vehicle signals, and identify a first satellite vehicle based on the first signal. The reconfiguration engine is configured to receive an indication that the acquisition engine identified the first satellite vehicle, and responsive to receiving the indication, generate a reconfiguration file defining a second circuit size less than the first circuit size. The reconfiguration engine is configured to cause the acquisition engine to be reconfigured based on the reconfiguration file to use the second circuit size.

Abstract: A semiconductor package system is disclosed. The system includes a first interposer and a first integrated circuit die electrically coupled and thermally coupled to a first side of the first interposer. The system further includes a second integrated circuit die electrically coupled and thermally coupled to a second side of the first interposer. The system further includes a ring carrier electrically coupled and thermally coupled to the first interposer. The ring carrier is configured to transmit an input to the first interposer. In some embodiments, the system further includes at least one thermal spreader thermally coupled to the ring carrier and at least one of the first integrated circuit, the second integrated circuit, or the first interposer.

Abstract: A chip-scale gyrometric apparatus is disclosed. In embodiments, the chip-scale gyrometric apparatus includes a dielectric substrate and an antenna element attached thereto for receiving an inbound signal having an initial phase. The apparatus includes a splitter for splitting the inbound signal into two equivalent signals, and two coils connected to the splitter. The first coil carries one of the split signals in a clockwise (CW) path relative to a rotational axis, while the second coil carries the other split signal in a counterclockwise (CCW) path relative to the same axis. An integrated circuit (IC) on the substrate and connected to the first and second coils measures a phase shift between the first and second signals (e.g., deviation from the initial phase) based on their respective CW and CCW paths and determines, based on the measured phase shift, a degree of rotation relative to the common rotational axis.

Abstract: An electronic assembly is disclosed. The electronic assembly includes a primary die, comprising a bulk layer, an integrated circuitry layer, a metal layer, a first redistribution layer, and a first attachment layer. The primary die further includes at least one aligned through-hole in the bulk layer and integrated circuitry layer. The electronic assembly further includes a secondary die physically coupled to the primary die via a second attachment layer. The electronic assembly further includes an interconnect header that includes plurality of interconnect filaments configured to electrically couple the first redistribution layer to one of the at least one metal layer via the at least one bulk layer through-hole and the at least one integrated circuitry through-hole. The interconnect header is generated by applying an electrically conductive filaments on a plurality of wafers, thinning the wafers, stacking and attaching the wafers into a wafer stack, and dicing the wafer stack.

Abstract: An electronic assembly is disclosed. The electronic assembly includes a first attachment layer, a second attachment layer, a first interposer redistribution layer, a second interposer redistribution layer, at least one of a thermal spreader layer or a thermal management layer, and an interposer cavity. The interposer further includes an interconnect header fixed within the interposer cavity comprising a plurality of interconnect filaments configured to electrically couple to at least one of the first interposer redistribution layer or the second interposer redistribution layer. The interconnect header is generated by applying electrically conductive filaments on a plurality of wafers, thinning the wafers, stacking the wafers, attaching the wafers into a wafer stack, and dicing the wafer stack.

Abstract: A system is disclosed that includes an electronic package. The electronic package includes a package base couplable to a host substrate, and a package lid mechanically coupled to the package base that includes one or more transparent lid areas, configured to permit transmission of light. The electronic package further includes a thermal spreader bonded on a first side to a first side of the package lid. The thermal spreader includes one or more transparent spreader areas that are configured to allow transmission of light through the thermal spreader. The electronic package further includes one or more integrated circuits bonded to a second side of the thermal spreader that communicatively coupled to the host substrate. The electronic package further includes one or more optical paths that include at least one of the one or more transparent spreader areas configured adjacent to at least one of the transparent lid areas.

Abstract: A structural connector system for providing an electrical connection between electronic componentry is disclosed. The structural connector system includes a structural member, including an electrically insulating matrix, an electrically conducting path, a first end surface, a second end surface, and a first component engaging surface. The first component engaging surface includes a first mechanical coupler configured to mechanically couple a first electronic component or a first chassis component to the structural member and a first electrical coupler configured to electrically couple the first electronic component or the first chassis component to a first end of the electrically conducting path.

Abstract: A system-in-package (SiP) incorporating] is disclosed. In embodiments, the host die defines a substantially horizontal plane (e.g., via its active side). One or more vertical dielets are attached to, and interconnected with, the active side of the host die in a substantially vertical configuration (e.g., perpendicular to the host die). Due to the perpendicular orientation of the dielets, the SiP incorporates thermal spreaders in thermal contact with the active side of the host die as well as the inactive sides of the dielets, allowing for thermal dissipation from the host dies and dielets without the need for through silicon vias.

Abstract: A redundant processing system with profile-based monitoring is disclosed. In embodiments, the redundant system includes two or more redundant lanes, each lane having equivalent processing components. In a testing state, template processors and hardware monitoring sensors are connected to a selected trusted lane and input vectors submitted thereto; the hardware sensors characterize the response of the selected lane and the resulting testing data compiled into system templates. In an operational environment, the template processors send challenges based on the input vectors to each of the redundant lanes in real time, collecting response data from each lane via identical sets of monitoring sensors. The template processors correlate the response data with the corresponding system templates, identifying anomalous lanes and system anomalies based on discorrelations between the response data and the system templates.

Abstract: A runtime monitoring system for a trusted computing environment is disclosed. In embodiments, the environment includes a trusted processor driven by a primary oscillator and a remote processing component driven by an auxiliary oscillator. A trusted reference hashing module hashes operating codes sent by the trusted processor for execution by the remote processing component; the received operating codes are also hashed by a trusted remote hashing module monitoring the remote processing component. A correlation module matches the remote and reference hashes and advances or delays the auxiliary oscillator to loop-lock the remote processing component to the trusted processor. The trusted processor periodically seeds the operating codes with a unique challenge having a unique hash response.

Abstract: A semiconductor package system is disclosed. The system includes a first interposer and a first integrated circuit die electrically coupled and thermally coupled to a first side of the first interposer. The system further includes a second integrated circuit die electrically coupled and thermally coupled to a second side of the first interposer. The system further includes a ring carrier electrically coupled and thermally coupled to the first interposer. The ring carrier is configured to transmit an input to the first interposer. In some embodiments, the system further includes at least one thermal spreader thermally coupled to the ring carrier and at least one of the first integrated circuit, the second integrated circuit, or the first interposer.

Abstract: A hardware malware profiling and detection system is disclosed. In embodiments, the system includes a primary (e.g., trusted) system including template processors and hardware sensors. The template processors submit input vectors to the primary system and characterize the system response via power trace data collected by the hardware sensors. Based on the input vectors and power trace data, the template processors generate system templates and derive system challenges therefrom. The template processors submit the system challenges to a remote system under test and characterize the remote system response in real time via identical remote hardware sensors. The template processors correlate the real-time remote system response data with the system templates corresponding to the issued challenges to detect system anomalies or malware within the remote system or its components.

Abstract: A system and method for cross-domain parallel inspection of data packets in transit between domains of differing security classification incorporating sequential cryptographic control is disclosed. In embodiments, the system includes first and second random number generators, each generating a one-time pad for transmission to both a corresponding front-end cryptographic engine and a parallel guard engine. The cryptographic engines double encrypt the data packet in sequence according to the one-time pads, storing the encrypted packet in a holding register. Each guard engine inspects the data packet in parallel, indicating approval by transmitting a release to the holding register and sending its one-time pad to a back-end cryptographic engine. When the holding register receives both releases, the double encrypted packet is sequentially decrypted by the back-end cryptographic engines in reverse order according to the one-time pads received from the guard engines.