Patents by Inventor Reid T. Copeland

Reid T. Copeland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180095721
    Abstract: An instruction to perform a multiply and shift operation is executed. The executing includes multiplying a first value and a second value obtained by the instruction to obtain a product. The product is shifted in a specified direction by a user-defined selected amount to provide a result, and the result is placed in a selected location. The result is to be used in processing within the computing environment.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Jonathan D. Bradbury, Steven R. Carlough, Reid T. Copeland, Silvia Melitta Mueller
  • Publication number: 20180095724
    Abstract: An instruction to perform a shift and divide operation is executed. The executing includes shifting a value in a specified direction by a selected amount to provide a dividend, the selected amount being user-defined. The dividend is divided by a divisor to obtain a quotient. At least a subset of the quotient is selected as a result. The result is to be used in processing within the computing environment.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Jonathan D. Bradbury, Steven R. Carlough, Reid T. Copeland, Silvia Melitta Mueller, Eric M. Schwarz
  • Publication number: 20180095757
    Abstract: An instruction generates a value for use in processing within a computing environment. The instruction obtains a sign control associated with the instruction, and shifts an input value of the instruction in a specified direction by a selected amount to provide a result. The result is placed in a first designated location in a register, and the sign, which is based on the sign control, is placed in a second designated location of the register. The result and the sign provide a signed value to be used in processing within the computing environment.
    Type: Application
    Filed: November 8, 2017
    Publication date: April 5, 2018
    Inventors: Jonathan D. Bradbury, Reid T. Copeland, Silvia Melitta Mueller
  • Publication number: 20180095723
    Abstract: An instruction to perform a multiply and shift operation is executed. The executing includes multiplying a first value and a second value obtained by the instruction to obtain a product. The product is shifted in a specified direction by a user-defined selected amount to provide a result, and the result is placed in a selected location. The result is to be used in processing within the computing environment.
    Type: Application
    Filed: November 8, 2017
    Publication date: April 5, 2018
    Inventors: Jonathan D. Bradbury, Steven R. Carlough, Reid T. Copeland, Silvia Melitta Mueller
  • Publication number: 20180095727
    Abstract: An instruction to perform a sign operation of a plurality of sign operations configured for the instruction. The instruction is executed, and the executing includes selecting at least a portion of an input operand as a result to be placed in a select location. The selecting is based on a control of the instruction, in which the control indicates a user-defined size of the input operand to be selected as the result. A sign of the result is determined based on a plurality of criteria, including a value of the result, obtained based on the control of the instruction, having a first particular relationship or a second particular relationship with respect to a selected value. The result and the sign are stored in the select location to provide a signed output to be used in processing within the computing environment.
    Type: Application
    Filed: November 8, 2017
    Publication date: April 5, 2018
    Inventors: Jonathan D. Bradbury, Reid T. Copeland, Silvia Melitta Mueller, Timothy J. Slegel
  • Patent number: 9921814
    Abstract: A method and systems generate a control flow graph including an edge of the control flow graph from a branch instruction to a target address of the branch instruction in an abstract interpretation for an assignment instruction to a branch target variable of a program. The program allocates a particular branch target variable to a branch instruction having a plurality of branch targets. The branch target address is loaded from the branch target variable upon branching, a branch address of a branch instruction having one branch target as well as the address assigned by the assignment instruction to the branch target variable being determined as certain constant values determined by compiling the program. The target address assigned by the assignment instruction is added to an object of the abstract interpretation. A current abstract interpretation is terminated if the abstract interpretation reaches an instruction already subjected to the abstract interpretation.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Reid T. Copeland, Toshihiko Koju
  • Patent number: 9916143
    Abstract: Arrangements described herein relate to inserting implicit sequence points into computer program code to support debug operations. Optimization of the computer program code can be performed during compilation of the computer program code and, during the optimization, implicit sequence points can be inserted into the computer program code. The implicit sequence points can be configured to provide virtual reads of symbols contained in the computer program code when the implicit sequence points are reached during execution of the computer program code during a debug operation performed on the computer program code after the computer program code is optimized and compiled.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: March 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher E. Bowler, Chen Chen, Reid T. Copeland, Tommy U. Hoffner, Tarique M. Islam, Raúl E. Silvera
  • Patent number: 9910648
    Abstract: Arrangements described herein relate to inserting implicit sequence points into computer program code to support debug operations. Optimization of the computer program code can be performed during compilation of the computer program code and, during the optimization, implicit sequence points can be inserted into the computer program code. The implicit sequence points can be configured to provide virtual reads of symbols contained in the computer program code when the implicit sequence points are reached during execution of the computer program code during a debug operation performed on the computer program code after the computer program code is optimized and compiled.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: March 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher E. Bowler, Chen Chen, Reid T. Copeland, Tommy U. Hoffner, Tarique M. Islam, Raúl E. Silvera
  • Publication number: 20180032321
    Abstract: Optimization of computer program code can be performed during compilation of the computer program code. During the compilation of the computer program code, at least a first location in the computer program code that performs a calculation on at least one parameter value that affects a user experience provided by the computer program code can be automatically determined. During the optimization, a first implicit sequence point can be inserted into the computer program code at the automatically determined first location, wherein the first implicit sequence point is configured to provide a virtual read of at least a first symbol contained in the computer program code when the first implicit sequence point is reached during execution of the computer program code during a debug operation performed on the computer program code after the computer program code is optimized and compiled.
    Type: Application
    Filed: October 7, 2017
    Publication date: February 1, 2018
    Inventors: Christopher E. Bowler, Chen Chen, Reid T. Copeland, Tommy U. Hoffner, Tarique M. Islam, Raúl E. Silvera
  • Publication number: 20170060589
    Abstract: A method and systems generate a control flow graph including an edge of the control flow graph from a branch instruction to a target address of the branch instruction in an abstract interpretation for an assignment instruction to a branch target variable of a program. The program allocates a particular branch target variable to a branch instruction having a plurality of branch targets. The branch target address is loaded from the branch target variable upon branching, a branch address of a branch instruction having one branch target as well as the address assigned by the assignment instruction to the branch target variable being determined as certain constant values determined by compiling the program. The target address assigned by the assignment instruction is added to an object of the abstract interpretation. A current abstract interpretation is terminated if the abstract interpretation reaches an instruction already subjected to the abstract interpretation.
    Type: Application
    Filed: August 24, 2015
    Publication date: March 2, 2017
    Inventors: REID T. COPELAND, TOSHIHIKO KOJU
  • Patent number: 9563536
    Abstract: Without using a high-level programming language source code, a set of sync points is identified in an initial binary code. The initial binary code is executed at a first system. A value of the user data is captured from a user space of a memory as a baseline of the user data. A set of comparative sync points is identified in a second binary code. During an execution of the second binary code, a second value of the user data from a second user space of a second memory is found to fail in matching the baseline of the user data. An instruction before the comparative sync point in the second binary code is identified as a location of a faulty operation due to the failing.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: February 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven Cooper, Reid T. Copeland, Toshihiko Koju, Roger H. E. Pett, Trong Truong
  • Publication number: 20160210151
    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.
    Type: Application
    Filed: March 28, 2016
    Publication date: July 21, 2016
    Inventors: Steven R. CARLOUGH, Reid T. COPELAND, Charles W. GAINEY, JR., Marcel MITRAN, Eric M. SCHWARZ, Timothy J. SLEGEL
  • Publication number: 20160210152
    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.
    Type: Application
    Filed: March 29, 2016
    Publication date: July 21, 2016
    Inventors: Steven R. CARLOUGH, Reid T. COPELAND, Charles W. GAINEY, JR., Marcel MITRAN, Eric M. SCHWARZ, Timothy J. SLEGEL
  • Publication number: 20160210144
    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.
    Type: Application
    Filed: March 29, 2016
    Publication date: July 21, 2016
    Inventors: Steven R. CARLOUGH, Reid T. COPELAND, Charles W. GAINEY, Jr., Marcel MITRAN, Eric M. SCHWARZ, Timothy J. SLEGEL
  • Publication number: 20160210143
    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.
    Type: Application
    Filed: March 28, 2016
    Publication date: July 21, 2016
    Inventors: Steven R. CARLOUGH, Reid T. COPELAND, Charles W. GAINEY, JR., Marcel MITRAN, Eric M. SCHWARZ, Timothy J. SLEGEL
  • Publication number: 20160154636
    Abstract: Arrangements described herein relate to inserting implicit sequence points into computer program code to support debug operations. Optimization of the computer program code can be performed during compilation of the computer program code and, during the optimization, implicit sequence points can be inserted into the computer program code. The implicit sequence points can be configured to provide virtual reads of symbols contained in the computer program code when the implicit sequence points are reached during execution of the computer program code during a debug operation performed on the computer program code after the computer program code is optimized and compiled.
    Type: Application
    Filed: February 4, 2016
    Publication date: June 2, 2016
    Inventors: Christopher E. Bowler, Chen Chen, Reid T. Copeland, Tommy U. Hoffner, Tarique M. Islam, Raúl E. Silvera
  • Publication number: 20160154637
    Abstract: Arrangements described herein relate to inserting implicit sequence points into computer program code to support debug operations. Optimization of the computer program code can be performed during compilation of the computer program code and, during the optimization, implicit sequence points can be inserted into the computer program code. The implicit sequence points can be configured to provide virtual reads of symbols contained in the computer program code when the implicit sequence points are reached during execution of the computer program code during a debug operation performed on the computer program code after the computer program code is optimized and compiled.
    Type: Application
    Filed: February 4, 2016
    Publication date: June 2, 2016
    Inventors: Christopher E. Bowler, Chen Chen, Reid T. Copeland, Tommy U. Hoffner, Tarique M. Islam, Raúl E. Silvera
  • Patent number: 9335995
    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: May 10, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Reid T. Copeland, Charles W. Gainey, Jr., Marcel Mitran, Eric M. Schwarz, Timothy J. Slegel
  • Patent number: 9335993
    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: May 10, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Reid T. Copeland, Charles W. Gainey, Jr., Marcel Mitran, Eric M. Schwarz, Timothy J. Slegel
  • Patent number: 9335994
    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: May 10, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Reid T. Copeland, Charles W. Gainey, Jr., Marcel Mitran, Eric M. Schwarz, Timothy J. Slegel