Abstract: A monolithic sensor arrangement includes a housing, a sensor integrated in the housing, and two or three connecting contacts deployed on the housing so as to provide a contact with the sensor. The housing also includes an integrated digital circuit includes a freely programmable digital processor, a program memory and a data memory, which are used to control and/or process the functionalities and/or the measured data of the sensor.

Abstract: A semiconductor component on a semiconductor chip comprises at least one sensor element for measuring a physical quantity and an evaluator. The semiconductor component can be switched between a first and a second operating mode. In the first operating mode, the sensor element is sensitive to the physical quantity to be measured and a measurement signal output of the sensor element is connected to an input connection of the evaluator. In the second operating mode, the sensor element is not sensitive to the physical quantity to be measured and/or the signal path between the measurement signal output and the input connection is interrupted. A test signal source for generating a test signal simulating the measurement signal of the sensor element is arranged on the semiconductor chip. In the second operating mode, the test signal source is connected or capable of being connected to the input connection of the evaluator.

Abstract: Disclosed is a method and device for transmitting data between at least two transmitters and a receiver which are connected to a bus. A synchronization signal is applied to the bus and a number of data volume counters corresponding to the number of transmitters reduced by one is set to a predefined initial value. A first transmitter transmits in the form of data elements a predefined data volume allocated to the transmitter over the bus to the receiver. The data volume values of the other transmitters are selected so that only one transmitter at any given time simultaneously transmits on the bus.

Abstract: Disclosed is an integrated electronic circuit comprising a core circuit that generates a useful signal as well as a buffer for storing the useful signal. The buffer stores the last read value of the useful signal for a predetermined period of time when the power supply is interrupted, and the buffer is disconnected from the power supply of the other circuits.

Abstract: A semiconductor component has at least one semiconductor chip in which an electrical circuit is integrated. The semiconductor chip is surrounded by an electrically insulating encapsulating compound and has on its surface at least one termination surface for a test signal, which is covered by the encapsulating compound. The termination surface is connected in an electrically conductive manner to an analysis contact that projects above the surface of the semiconductor chip, that is located in the interior of the encapsulating compound at a distance from its exterior surface, and that can be exposed by removing a layer of the encapsulating compound located near the exterior.

Abstract: A method and circuitry for checking the programming (P) and deletion (L) operations of memory cells (5) in a nonvolatile memory device (1). Parallel to the programming (P) or deletion (L) operations of the actual memory cells (5) the respective programming or deletion process is carried out on at least one similar checking cell (4.1, 4.2, 4.3), with the programming (P) or deletion (L) operations being less favorable by a defined extent than the programming (P) or deletion (L) operations of the actual memory cells (5). From the content of the checking cell (4.1, 4.2, 4.3) an evaluation device (6) determines whether the programming (P) or deletion (L) operation was successful or not, and a corresponding output signal (ak) indicative thereof is produced.

Abstract: A digital-to-analog converter circuit layout includes a ratiometric digital-to-analog converter. The ratiometric digital-to-analog converter includes a digital data input, a converter voltage output, a voltage controlled oscillator, and a pulse width modulation module. The a digital data input, a converter voltage output, a voltage controlled oscillator, and a pulse width modulation module is configured in a controllable manner for converting digital data received at the input to a converter output voltage at the output using a reference voltage, an adjustable current as a reference current, and an adjustable impedance value. The circuit layout is characterized in that the voltage controlled oscillator includes circuit components which multiply the reference voltage by a quotient between the adjustable impedance value and the adjustable current, and which apply the multiplication results to the pulse width modulation module.

Abstract: The invention relates to a circuit configuration with a serial test interface (TIF) to control a test operation mode, a freely programmable digital processor (CPU), a housing (G) for the accommodation of a test interface (TIF) and the processor (CPU) with terminals or connectors (C0, C1) for data and/or signal exchange with external components and setups. At one of the terminals (C1), a modulated supply voltage (VDD) can be received the transfer of data (d) and or a clock (T) by using at least two voltage levels (V2, V3) that can be controlled and which are different from a supply voltage level (V1) that is designed to feed the circuitry with a supply operating voltage. Furthermore, the invention relates to a serial test operation method for such a circuit configuration.

Abstract: A digital-to-analog converter circuit layout includes a ratiometric digital-to-analog converter. The ratiometric digital-to-analog converter includes a digital data input, a converter voltage output, a voltage controlled oscillator, and a pulse width modulation module. The a digital data input, a converter voltage output, a voltage controlled oscillator, and a pulse width modulation module is configured in a controllable manner for converting digital data received at the input to a converter output voltage at the output using a reference voltage, an adjustable current as a reference current, and an adjustable impedance value. The circuit layout is characterized in that the voltage controlled oscillator includes circuit components which multiply the reference voltage by a quotient between the adjustable impedance value and the adjustable current, and which apply the multiplication results to the pulse width modulation module.

Abstract: Disclosed is a method and device for transmitting data between at least two transmitters and a receiver which are connected to a bus. A synchronization signal is applied to the bus and a number of data volume counters corresponding to the number of transmitters reduced by one is set to a predefined initial value. A first transmitter transmits in the form of data elements a predefined data volume allocated to the transmitter over the bus to the receiver. The data volume values of the other transmitters are selected so that only one transmitter at any given time simultaneously transmits on the bus.

Abstract: A semiconductor component (has at least one semiconductor chip in which an electrical circuit is integrated. The semiconductor chip is surrounded by an electrically insulating encapsulating compound and has on its surface at least one termination surface for a test signal, which is covered by the encapsulating compound. The termination surface is connected in an electrically conductive manner to an analysis contact that projects above the surface of the semiconductor chip, that is located in the interior of the encapsulating compound at a distance from its exterior surface, and that can be exposed by removing a layer of the encapsulating compound located near the exterior.

Abstract: The invention relates to integrated circuits comprising a monolithically integrated logic IC and a monolithically integrated interface circuit that is conductively connected to the logic IC. The electrical properties of said interface circuit are programmable. The interface circuit also has a lower integration density than the logic IC, and comprises monitoring modules for monitoring the logic ICs.

Abstract: Disclosed is an integrated electronic circuit comprising a core circuit that generates a useful signal as well as a buffer for storing the useful signal. The buffer stores the last read value of the useful signal for a predetermined period of time when the power supply is interrupted, and the buffer is disconnected from the power supply of the other circuits.

Abstract: A method for testing a Hall magnetic field sensor on a wafer includes generating a current flow in a Hall plate of the Hall magnetic field sensor. At least one voltage value across first and second nodes is measured and a measured voltage signal is provided indicative thereof. An electrical resistance based upon the measured voltage and the current is then determined, in the absence of an applied test magnet field.

Abstract: A monolithic sensor arrangement includes a housing, a sensor integrated in the housing, and two or three connecting contacts deployed on the housing so as to provide a contact with the sensor. The housing also includes an integrated digital circuit includes a freely programmable digital processor, a program memory and a data memory, which are used to control and/or process the functionalities and/or the measured data of the sensor.

Abstract: A semiconductor component on a semiconductor chip comprises at least one sensor element for measuring a physical quantity and an evaluator. The semiconductor component can be switched between a first and a second operating mode. In the first operating mode, the sensor element is sensitive to the physical quantity to be measured and a measurement signal output of the sensor element is connected to an input connection of the evaluator. In the second operating mode, the sensor element is not sensitive to the physical quantity to be measured and/or the signal path between the measurement signal output and the input connection is interrupted. A test signal source for generating a test signal simulating the measurement signal of the sensor element is arranged on the semiconductor chip. In the second operating mode, the test signal source is connected or capable of being connected to the input connection of the evaluator.

Abstract: The invention relates to a circuit configuration with a serial test interface (TIF) to control a test operation mode, a freely programmable digital processor (CPU), a housing (G) for the accommodation of a test interface (TIF) and the processor (CPU) with terminals or connectors (C0, C1) for data and/or signal exchange with external components and setups. At one of the terminals (C1), a modulated supply voltage (VDD) can be received the transfer of data (d) and or a clock (T) by using at least two voltage levels (V2, V3) that can be controlled and which are different from a supply voltage level (V1) that is designed to feed the circuitry with a supply operating voltage. Furthermore, the invention relates to a serial test operation method for such a circuit configuration.

Abstract: A method and circuitry for checking the programming (P) and deletion (L) operations of memory cells (5) in a nonvolatile memory device (1). Parallel to the programming (P) or deletion (L) operations of the actual memory cells (5) the respective programming or deletion process is carried out on at least one similar checking cell (4.1, 4.2, 4.3), with the programming (P) or deletion (L) operations being less favorable by a defined extent than the programming (P) or deletion (L) operations of the actual memory cells (5). From the content of the checking cell (4.1, 4.2, 4.3) an evaluation device (6) determines whether the programming (P) or deletion (L) operation was successful or not, and a corresponding output signal (ak) indicative thereof is produced.

Abstract: A method for testing a Hall magnetic field sensor on a wafer includes generating a current flow in a Hall plate of the Hall magnetic field sensor. At least one voltage value across first and second nodes is measured and a measured voltage signal is provided indicative thereof. An electrical resistance based upon the measured voltage and the current is then determined, in the absence of an applied test magnet field.

Abstract: To suppress oscillation modes, in particular, higher-order oscillation modes, in a ring oscillator comprising delay elements forming the oscillator ring and being linked by nodes in the ring, and further comprising a gate element located in the oscillator ring which is activated by a control signal to open and close the gate element, the control signal is derived from at least one of the levels of the oscillator signal at the nodes. The control signal is such that the normal oscillation mode, that is, the fundamental oscillation and/or another desired higher-order oscillation, is not affected by the gate. However, unwanted oscillation modes (e.g., the higher oscillation modes) are effectively suppressed in the case of the fundamental oscillation representing the normal oscillation mode.