Abstract: The present disclosure is directed to apparatuses and methods to pre-compensate and/or post-compensate for inter-symbol interference (ISI). The apparatuses and methods of the present disclosure can be implemented as part of an I/O interface in a memory or memory controller, including dynamic random access memory (DRAM).

Abstract: A cache memory controller in which data processing systems having active power management may efficiently flush a cache during a shut down operation. A cache map divides the cache into a number of blocks and an inclusion bit is stored for each block. The block inclusion bit is set whenever a cache line in the block is fetched. As a result, when it is time to flush the cache during a time critical power management operation, the software need only flush those sections of the cache where the block inclusion bit has been set.

Abstract: A memory controller for optimizing direct memory access (DMA) read transactions wherein a number of cache lines are prefetched from a main memory as specified in a prefetch length field stored in a page table. When all prefetch data has been fetched, the memory controller waits to determine whether the initiator of the DMA read transaction will request additional data. If additional data is needed, additional cache lines are fetched. Once the initiator terminates the DMA read transaction, the prefetch length field for a selected page other entry in the table is updated to reflect the actual DMA read transaction length. As a result, an optimum number of cache lines are always prefetched thereby reducing the number of wait states required.

Abstract: A technique for implementing a programmable thermal model of an integrated circuit component such as a central processing unit (CPU) and its associated heat sink. The model estimates the die temperature of the component as if there were no cooling devices present in the system such as a forced air cooling fan by integrating the thermal energy added when the component is active and by integrating the thermal energy removed when it is idle. A programmable power value may be used to represent the heat added to the model at each model sample period. The effect of a heat sink in cooling the idle component may be modeled by reducing the value of the heat accumulator by a predetermined fractional amount during each sample period. The decay time constant for the model may be changed by then adjusting the sample period.

Abstract: A memory controller such as for use with a synchronous dynamic random access memory (SDRAM) wherein an active row at the end of each transfer can either be left active or closed by precharging the row. The memory controller uses a history register to keep track of the results of a number of prior accesses to each memory bank, remembering whether the access was to the same row as an immediately prior access. For each new memory access, the memory controller either asserts or deasserts a precharge enable signal depending on the state of the history bits. As a result, the memory controller is more likely to have a correct row open on a subsequent access, and less likely to have a wrong row open.