Abstract: Described herein is a rate controller in a video system. The rate controller estimates a bit count, and controls three adaptive rate control loops. The master rate control loop is in control of the quantizer. The slave rate control loops control coarse motion estimation and fine motion estimation.

Abstract: According to one exemplary embodiment, a termination circuit includes a number of drivers configured to receive source data on an input bus and to drive an output bus including a number of output lines. In the termination circuit the output lines are terminated by resistors, where one resistor is coupled between each output line and a common capacitor node. The termination circuit further includes a virtual regulator at the drivers, configured to control a termination voltage at the capacitor node by inputting compensation data into the drivers during idle cycles to achieve a net average 50% duty cycle. The virtual regulator can determine which cycles are idle by detecting an idle code in the source data.

Abstract: A system and method that process data in a circuitry utilizing two clocks. The two clocks may be an offset version of one another. Utilizing two clocks to processes the data may consume fewer clock cycles than using only one clock. The circuitry may comprise registers and a memory, wherein one register may receive a location of information in the memory, which may then be read from the received location. The one register may utilize a first of the two clocks, and the reading from the memory may utilize the second of the two clocks. The circuitry may comprise a portion of a CABAC decoder.

Abstract: Presented herein is a system and apparatus for accelerating arithmetic decoding of encoded data. In one embodiment, there is presented a symbol interpreter for decoding CABAC coded data. The symbol interpreter comprises a first memory, a CABAC decoding loop, and a syntax assembler. The first memory receives a bitstream comprising the CABAC coded data at a channel rate. The CABAC decoding loop decodes the CABAC symbols at the channel rate, and comprises an arithmetic decoder for generating binary symbols from the CABAC coded data at the channel rate. The syntax assembler decodes the binary symbols at a consumption rate.

Abstract: In one embodiment, there is presented an integrated circuit. The integrated circuit comprises a transport processor and a host processor. The transport processor parses a media stream. The host processor determines whether a media stream is Blu-ray or HD-DVD and configures the transport processor based on whether the media stream is Blu-ray or HD-DVD.

Abstract: Described herein are a method and system for memory access. As the complexity of digital signal processing applications increases, designs may require multiple memory chips. To optimize the bandwidth of the data being accessed from the memory chips, blocks of data are read alternatively from each memory chip. The size of a block of data is determined by the bit width of a word and the number or memory arrays in a chip.

Abstract: A system and method for automatically tuning timing of a signal (e.g., a data timing signal) utilizing determined delay of a variable delay element and for utilizing such a tuned signal. Various aspects of the invention may comprise experimentally determining delay characteristics of an on-chip variable delay circuit utilizing an on-chip test module. A delay control signal for an on-chip variable delay circuit may be determined based at least in part on the experimentally determined delay characteristics. Timing of a signal may be adjusted by inputting the signal and the delay control signal into the on-chip variable delay circuit. The time-adjusted signal may then be utilized in signal processing. Such signal processing may, for example, comprise receiving an input data timing signal, generating a delayed input data timing signal, and generating an output data timing signal based on the input data timing signal and the delayed input data timing signal.

Abstract: Described herein are a method and system for memory access. As the complexity of digital signal processing applications increases, designs may require multiple memory chips. To optimize the bandwidth of the data being accessed from the memory chips, blocks of data are read alternatively from each memory chip. The size of a block of data is determined by the bit width of a word and the number or memory arrays in a chip.

Abstract: Described herein is a rate controller in a video system. The rate controller estimates a bit count, and controls three adaptive rate control loops. The master rate control loop is in control of the quantizer. The slave rate control loops control coarse motion estimation and fine motion estimation.

Abstract: Described herein is a context adaptive binary arithmetic code decoder for decoding macroblock adaptive field/frame coded video data. In one embodiment, there is presented a video system. The video system comprises a CABAC decoder and neighbor buffer. The CABAC decoder decodes CABAC symbols associated with a portion of a picture, thereby resulting in decoded CABAC symbols. The neighbor buffer stores information from decoded CABAC symbols associated with another portion of the picture, said another portion being adjacent to the portion. The CABAC decoder decodes the CABAC symbols based on the information about the another portion of the picture.

Abstract: A system and method for automatically tuning timing of a signal (e.g., a data timing signal) utilizing determined delay of a variable delay element and for utilizing such a tuned signal. Various aspects of the invention may comprise experimentally determining delay characteristics of an on-chip variable delay circuit utilizing an on-chip test module. A delay control signal for an on-chip variable delay circuit may be determined based at least in part on the experimentally determined delay characteristics. Timing of a signal may be adjusted by inputting the signal and the delay control signal into the on-chip variable delay circuit. The time-adjusted signal may then be utilized in signal processing. Such signal processing may, for example, comprise receiving an input data timing signal, generating a delayed input data timing signal, and generating an output data timing signal based on the input data timing signal and the delayed input data timing signal.

Abstract: A system and method that process data in a circuitry utilizing two clocks. The two clocks may be an offset version of one another. Utilizing two clocks to processes the data may consume fewer clock cycles than using only one clock. The circuitry may comprise registers and a memory, wherein one register may receive a location of information in the memory, which may then be read from the received location. The one register may utilize a first of the two clocks, and the reading from the memory may utilize the second of the two clocks. The circuitry may comprise a portion of a CABAC decoder.

Abstract: Presented herein is a system and apparatus for accelerating arithmetic decoding of encoded data. In one embodiment, there is presented a decoder system for decoding compressed video data. The decoder comprises a host processor, a first decoder engine, and a second decoder engine. The host processor finds a first portion of the compressed video data and a second portion of the compressed video data. The first portion of the compressed video data and the second portion of the compressed video data are data independent from each other. The first decoder engine decodes the first portion of the video data. The second decoder engine decodes the second portion of the video data, while the first decoder engine decodes the first portion of the video data.

Abstract: Presented herein is a system and apparatus for accelerating arithmetic decoding of encoded data. In one embodiment, there is presented a symbol interpreter for decoding CABAC coded data. The symbol interpreter comprises a first memory, a CABAC decoding loop, and a syntax assembler. The first memory receives a bitstream comprising the CABAC coded data at a channel rate. The CABAC decoding loop decodes the CABAC symbols at the channel rate, and comprises an arithmetic decoder for generating binary symbols from the CABAC coded data at the channel rate. The syntax assembler decodes the binary symbols at a consumption rate.

Abstract: A computer system including a microprocessor and a circuit to provide a clock signal for the microprocessor is described. The circuit is responsive to a control signal for selecting a minimum clock signal frequency value and a maximum clock signal frequency value, with the maximum clock signal frequency value being adjusted in accordance with operating conditions of the central processor. Also the system includes a circuit which varies a magnitude of a supply voltage fed to the microprocessor in accordance with the temperature of the microprocessor and the operating frequency of the microprocessor. This arrangement provides an advantage to save power in computers. It is particularly advantageous for portable computers such as notebook computers to conserve battery charge, minimize heat dissipation in the microprocessor, and to minimize the size and weight of the battery used in the notebook for a given operating duration requirement.

Abstract: A method of performing continuity testing of individual lead sets bonded to an integrated semiconductor component with a continuity test circuit fabricated on the component. The continuity test circuit includes a plurality of current gates, each of which is associated with a different semiconductor component contact pad a lead set is bonded to. Each current gate includes a first terminal connected to the associated contact pad and a second terminal connected to a common conductor all the current gate second terminals are connected to. The common conductor terminates at a semiconductor component contact test pad a lead set is bonded to. Whenever a test signal is applied to either the first or second terminal of a current gate, a measurable response signal is generated by the current gate over the other terminal.

Abstract: A bus device is provided for use in a data processing system which includes a plurality of bus devices interconnected by a synchronous bus. The bus includes multiplexed data/address/arbitration lines which carry data, address, and arbitration information during respective data, command/address, and arbitration cycles. The bus also includes a BUSY line and a NO ARB line for controlling access to the data/address/arbitration lines. Where constructed as a memory device, the bus device includes memory circuits having a plurality of storage locations, and an interconnecting circuit which monitors the BUSY and NO ARB lines to identify various types of cycles on the bus, and which controls transmission of signals from the memory device over the bus in accordance with information derived by the monitoring means from the BUSY and NO ARB lines.

Abstract: Control of a communications path interconnecting separate devices in a digital computer system is provided by only two signals generated and received locally within each device on the path and asserted on a systems-wide basis on two separate lines of the path. The generation and utilization of the control signals is independent of the physical location of the devices on the path, and position-dependent delays in transmission of the signals from one device to another are avoided.

Abstract: One of a plurality of devices on a common communications path (68) has a local memory (54) that is accessible by other devices on the common communications path (68). Another device on the common communications path (68) may include a cache memory (190) that keeps copies of certain of the data contained by the local memory (54). If another device on the common communications path (68) accesses the local memory (54), the cache (190) is kept apprised of this fact by monitoring of the common communications path (68), and it sets an internal flag to indicate that the data involved may not be valid. However, the contents of memory 54 may also be accessed by means of a processor (50) without using the common communications path (68). Accordingly, provisions are made to send an invalidate signal over the common communications path (68) when a non-path access of the local memory (54) has been made to a location to which access was previously afforded over the common communications path ( 68).

Abstract: A data processing system including a central processing unit and external memory. The central processing unit has an arithmetic logic unit having first and second inputs and an output for outputting data. The arithmetic logic unit inputs are selectively connected to the outputs of a plurality of addressable registers which registers have inputs connectable to the arithmetic logic unit output for receiving and storing data therefrom. Additionally, the central processing unit has a read only memory capable of storing a plurality of addressable control instructions and having a plurality of outputs for supplying control signals in dependence upon the addressed control instructions and means capable of addressing control instructions stored in the read only memory in a predetermined sequence, or addressing a selected one of said word locations in dependence upon the data outputted from the arithmetic logic unit.