Abstract: A grayscale morphological erosion operator image processor which operates on images of any size and dimension with a structuring element of any dimension and shape. The present invention performs all 1D erosion operations in the domain by first decomposing an image and structuring element into a series of 1D slices, and then further segmenting the structuring element into a plurality of shorter 1D segments. These segments are processed in parallel using an array of parallel processors. Once the erosion operations are complete, the resulting one dimensional slices are composed into a final eroded image.

Abstract: A binary morphological erosion operator image processor which operates on images of any size and dimension with a structuring element of any dimension and shape. The erosion operations are all processed in the 1D domain by first decomposing the image and structuring element into a series of 1D slices, and then further segmenting the structuring element into a plurality of shorter 1D segments. These segments are processed in parallel using an array of parallel processors. Once the erosion operations are completed, the resulting 1D slices are composed into a final eroded image.

Abstract: This invention relates to a method for computing the average data transmission rate available in each channel in a data communication, TCP/IP system that utilizes in part cable television channels as the transmission media. The method employs a bandwidth manager and a test personal computer, both of which are connected to the cable channel system to determine the average bit rate through any channel in the system. By utilizing computers connected to the cable system to make bit rate measurements, the problems associated with having a low speed telephone link that dominates the measurement is avoided.

Abstract: An embedded system for preventing removal of a control circuit pack during programming of a flash memory. The embedded system includes a reset button to be pressed prior to unplugging the control circuit pack and an indicator for signaling when the control circuit pack may be safely removed or unplugged from a shelf. In the case in which the flash memory is uninterruptable, all of the interrupts, except for a power reset interrupt, are inhibited during programming of at least one block of the flash memory. Upon activating the reset button, if programming of the flash memory is completed, then the reset interrupt is invoked and an indicator is enabled thereby signaling that it is safe to remove the control circuit pack. Otherwise, if programming of the flash memory is in progress, then the reset interrupt, like all other interrupts, is inhibited. Alternatively, the flash memory may be interruptable.