Patents by Inventor Ren-Fen Tsui
Ren-Fen Tsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11895819Abstract: A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.Type: GrantFiled: December 8, 2022Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw
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Publication number: 20230225100Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.Type: ApplicationFiled: March 13, 2023Publication date: July 13, 2023Inventors: Fang Chen, Jhon Jhy Liaw, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu, Yen-Huei Chen
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Publication number: 20230103306Abstract: A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.Type: ApplicationFiled: December 8, 2022Publication date: April 6, 2023Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw
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Patent number: 11605637Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.Type: GrantFiled: June 11, 2021Date of Patent: March 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fang Chen, Jhon Jhy Liaw, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu, Yen-Huei Chen
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Patent number: 11532554Abstract: In some embodiments of the method, patterning the opening includes: projecting a radiation beam toward the second dielectric layer, the radiation beam having a pattern of the opening. In some embodiments of the method, the single-patterning photolithography process is an extreme ultraviolet (EUV) lithography process. In some embodiments of the method, filling the opening with the conductive material includes: plating the conductive material in the opening; and planarizing the conductive material and the second dielectric layer to form the first metal line from remaining portions of the conductive material, top surfaces of the first metal line and the second dielectric layer being planar after the planarizing.Type: GrantFiled: February 19, 2021Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw, Ying-Jhe Fu
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Patent number: 11527540Abstract: A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.Type: GrantFiled: June 3, 2020Date of Patent: December 13, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Dian-Sheg Yu, Jhon Jhy Liaw, Ren-Fen Tsui
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Publication number: 20220172999Abstract: A semiconductor device includes first and second semiconductor fins, first, second, third and fourth gate structures, and a dielectric structure. The first semiconductor fin and the second semiconductor fin are over a substrate. The first gate structure and the second gate structure respectively extend across the first semiconductor fin and the second semiconductor fin. The first gate structure has a longitudinal axis aligned with a longitudinal axis of the second gate structure. The dielectric structure interposes the first gate structure and the second gate structure. The third gate structure extends across the first and second semiconductor fins. The fourth gate structure extends across the first and second semiconductor fins. The third gate structure is between the fourth gate structure and the dielectric structure. The third gate structure has a maximal width greater than a maximal width of the four gate structure.Type: ApplicationFiled: February 14, 2022Publication date: June 2, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Dian-Sheg YU, Ren-Fen TSUI, Jhon-Jhy LIAW
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Patent number: 11251091Abstract: A semiconductor device includes a semiconductor fin, a gate cut region, a first gate structure and a second gate structure. The semiconductor fin extends from a substrate. The gate cut region extends in parallel with a longitudinal axis of the semiconductor fin and not overlaps the semiconductor fin. The first gate structure and the second gate structure extend across the semiconductor fin. The first gate structure is laterally between the gate cut region and the second gate structure along a direction parallel with the longitudinal axis of the semiconductor fin. The first gate structure has a greater width variation than the second gate structure.Type: GrantFiled: October 19, 2020Date of Patent: February 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon-Jhy Liaw
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Publication number: 20210375355Abstract: A memory device includes a plurality of memory cells located in a first region of the memory device. The memory cells include a first signal line, a first circuit located in the first region of the memory device, and a plurality of logic circuits located in a second region of the memory device. The second region and the first region have different design rules. The first circuit is configured to be selectively enabled and disabled. When the first circuit is enabled, the first signal line is electrically coupled in parallel with a second signal line.Type: ApplicationFiled: May 29, 2020Publication date: December 2, 2021Inventors: Dian-Sheg Yu, Jhon Jhy Liaw, Ren-Fen Tsui, Bing-Chian Lin
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Patent number: 11189340Abstract: A memory device includes a plurality of memory cells located in a first region of the memory device. The memory cells include a first signal line, a first circuit located in the first region of the memory device, and a plurality of logic circuits located in a second region of the memory device. The second region and the first region have different design rules. The first circuit is configured to be selectively enabled and disabled. When the first circuit is enabled, the first signal line is electrically coupled in parallel with a second signal line.Type: GrantFiled: May 29, 2020Date of Patent: November 30, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Dian-Sheg Yu, Jhon Jhy Liaw, Ren-Fen Tsui, Bing-Chian Lin
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Patent number: 11145660Abstract: A dual-port SRAM includes a substrate, first and second active regions over the substrate and oriented lengthwise generally along a first direction; first and second gate electrodes oriented lengthwise generally along a second direction perpendicular to the first direction. The first and second gate electrodes engage the first and second active regions to form first and second pass gate transistors, respectively. The dual-port SRAM further includes a first gate contact disposed over the first gate electrode and electrically connected to the first gate electrode and a first source/drain contact oriented lengthwise generally along the second direction. The first source/drain contact directly contacts source/drain features of the first and second pass gate transistors. A portion of the first gate contact and a portion of the first source/drain contact are at a same vertical level from a top surface of the substrate and are aligned along the first direction.Type: GrantFiled: July 31, 2019Date of Patent: October 12, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw, Bing-Chian Lin
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Publication number: 20210305260Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.Type: ApplicationFiled: June 11, 2021Publication date: September 30, 2021Inventors: Fang Chen, Jhon Jhy Liaw, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu, Yen-Huei Chen
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Publication number: 20210202370Abstract: In some embodiments of the method, patterning the opening includes: projecting a radiation beam toward the second dielectric layer, the radiation beam having a pattern of the opening. In some embodiments of the method, the single-patterning photolithography process is an extreme ultraviolet (EUV) lithography process. In some embodiments of the method, filling the opening with the conductive material includes: plating the conductive material in the opening; and planarizing the conductive material and the second dielectric layer to form the first metal line from remaining portions of the conductive material, top surfaces of the first metal line and the second dielectric layer being planar after the planarizing.Type: ApplicationFiled: February 19, 2021Publication date: July 1, 2021Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw, Ying-Jhe Fu
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Patent number: 11037934Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.Type: GrantFiled: June 24, 2019Date of Patent: June 15, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fang Chen, Jhon Jhy Liaw, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu, Yen-Huei Chen
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Publication number: 20210074635Abstract: A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer.Type: ApplicationFiled: November 17, 2020Publication date: March 11, 2021Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw
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Publication number: 20210057327Abstract: In some embodiments of the method, patterning the opening includes: projecting a radiation beam toward the second dielectric layer, the radiation beam having a pattern of the opening. In some embodiments of the method, the single-patterning photolithography process is an extreme ultraviolet (EUV) lithography process. In some embodiments of the method, filling the opening with the conductive material includes: plating the conductive material in the opening; and planarizing the conductive material and the second dielectric layer to form the first metal line from remaining portions of the conductive material, top surfaces of the first metal line and the second dielectric layer being planar after the planarizing.Type: ApplicationFiled: August 23, 2019Publication date: February 25, 2021Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw, Ying-Jhe Fu
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Patent number: 10930590Abstract: In some embodiments of the method, patterning the opening includes: projecting a radiation beam toward the second dielectric layer, the radiation beam having a pattern of the opening. In some embodiments of the method, the single-patterning photolithography process is an extreme ultraviolet (EUV) lithography process. In some embodiments of the method, filling the opening with the conductive material includes: plating the conductive material in the opening; and planarizing the conductive material and the second dielectric layer to form the first metal line from remaining portions of the conductive material, top surfaces of the first metal line and the second dielectric layer being planar after the planarizing.Type: GrantFiled: August 23, 2019Date of Patent: February 23, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw, Ying-Jhe Fu
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Publication number: 20210050269Abstract: A semiconductor device includes a semiconductor fin, a gate cut region, a first gate structure and a second gate structure. The semiconductor fin extends from a substrate. The gate cut region extends in parallel with a longitudinal axis of the semiconductor fin and not overlaps the semiconductor fin. The first gate structure and the second gate structure extend across the semiconductor fin. The first gate structure is laterally between the gate cut region and the second gate structure along a direction parallel with the longitudinal axis of the semiconductor fin. The first gate structure has a greater width variation than the second gate structure.Type: ApplicationFiled: October 19, 2020Publication date: February 18, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Dian-Sheg YU, Ren-Fen TSUI, Jhon-Jhy LIAW
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Publication number: 20210035986Abstract: A dual-port SRAM includes a substrate, first and second active regions over the substrate and oriented lengthwise generally along a first direction; first and second gate electrodes oriented lengthwise generally along a second direction perpendicular to the first direction. The first and second gate electrodes engage the first and second active regions to form first and second pass gate transistors, respectively. The dual-port SRAM further includes a first gate contact disposed over the first gate electrode and electrically connected to the first gate electrode and a first source/drain contact oriented lengthwise generally along the second direction. The first source/drain contact directly contacts source/drain features of the first and second pass gate transistors. A portion of the first gate contact and a portion of the first source/drain contact are at a same vertical level from a top surface of the substrate and are aligned along the first direction.Type: ApplicationFiled: July 31, 2019Publication date: February 4, 2021Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw, Bing-Chian Lin
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Patent number: 10847457Abstract: A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer.Type: GrantFiled: April 22, 2019Date of Patent: November 24, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw