Abstract: Boot firmware for a computing device can be modularly and dynamically composed to facilitate implementing changes and updates to a computing device's firmware. The firmware image can include a primary module, which is responsible for certain basic initializations, and a module list, which can include a listing of additional modules that are to be executed during the boot procedure. The module list can be used to identify and access the selected modules from a module library, such as via globally unique identifiers (GUIDs). Once acquired, the selected modules can be executed, taking into account required dependency modules (whether included in the selected modules or not) and configuration settings. The module library can be stored entirely locally (e.g., as part of a distributed firmware image), entirely remotely (e.g., accessible via network connection), or a mixture of locally and remotely.

Abstract: A method and a device for balancing a battery state are provided, in which the method includes executing a battery capacity balancing of a plurality of battery packs when voltage information of the plurality of battery packs is open circuit voltages or when balanced voltages of the plurality of battery packs are on the same curve fragment, such that balanced capacities of the plurality of battery packs can be calculated via aging voltage compensation parameters and/or aging capacity compensation parameters of the plurality of battery packs, and a capacity adjustment can be performed according to the balanced capacities. Therefore, the battery capacity balancing can be performed by obtaining voltages in different states, and the battery capacity of each battery pack can be accurately adjusted to achieve balance among the battery packs by taking the aging parameters of the battery packs into consideration.

Abstract: The present invention provides a storage device including a controller and methods for operating the storage device and the controller. A controller of a storage device may comprise: an interface controller; a memory controller; a processor configured to transmit downstream commands and upstream commands to the memory controller. The memory controller may be coupled between the interface controller and the processor and may comprise: a first command queue; a second command queue; and a tag generator. The memory controller may be configured to: store a first command received from the processor in the first command queue; store a second command received from the processor in the second command queue; and in response to a first access region of the first command overlapping a second access region of the second command in the second queue, assign an order tag to the second command based on a first serial number of the first command by the tag generator.

Abstract: The present invention discloses an instruction processing apparatus, including: a first register adapted to store address information; a second register adapted to store address space identification information; a decoder adapted to receive and decode a translation lookaside buffer flush instruction, where the translation lookaside buffer flush instruction indicates that the first register serves as a first operand, and the second register serves as a second operand; and an execution unit coupled to the first register, the second register, and the decoder and executing the decoded translation lookaside buffer flush instruction, so as to acquire address information from the first register, to acquire address space identification information from the second register, and to broadcast the acquired address, information and address space identification information on a bus coupled to the instruction processing apparatus, so that another processing unit coupled to the bus performs purging on a translation lookaside

Abstract: A battery estimation method is provided. The method includes obtaining a potential difference parameter term associated with an estimated absolute state-of-charge for determining a maximum load capable of continuous drawing for a duration of the battery. The potential difference parameter term includes a potential difference characteristic parameter, or the potential difference parameter term includes the potential difference characteristic parameter and a potential difference compensation parameter.

Abstract: Boot firmware for a computing device can be modularly and dynamically composed to facilitate implementing changes and updates to a computing device's firmware. The firmware image can include a primary module, which is responsible for certain basic initializations, and a module list, which can include a listing of additional modules that are to be executed during the boot procedure. The module list can be used to identify and access the selected modules from a module library, such as via globally unique identifiers (GUIDs). Once acquired, the selected modules can be executed, taking into account required dependency modules (whether included in the selected modules or not) and configuration settings. The module library can be stored entirely locally (e.g., as part of a distributed firmware image), entirely remotely (e.g., accessible via network connection), or a mixture of locally and remotely.

Abstract: A battery estimation method is provided. The method includes obtaining a potential difference parameter term associated with an estimated absolute state-of-charge for determining a maximum load capable of continuous drawing for a duration of the battery. The potential difference parameter term includes a potential difference characteristic parameter, or the potential difference parameter term includes the potential difference characteristic parameter and a potential difference compensation parameter.

Abstract: A first logic circuit included in a processor receives a first digital signal, where the first logic circuit includes a special purpose register, a comparator, and an adder, where the special purpose register stores a first resource balance for executing a smart contract, where the first digital signal includes a resource deduction quota corresponding to a code set in the smart contract. The first logic circuit reads the first resource balance from the special purpose register. The first logic circuit compares, using the comparator, the first resource balance with the resource deduction quota. In response to the first resource balance being greater than or equal to the resource deduction quota, the first logic circuit subtracts, using the adder, the resource deduction quota from the first resource balance to obtain a second resource balance. The first logic circuit stores the second resource balance in the special purpose register.

Abstract: A method includes recording a branch current and a terminal voltage of each of two parallel connected cells of a battery pack during the battery pack being switched from a charging or discharging state through a rest state to a balance state, to obtain an internal resistance of each cell, and an open-circuit voltage (OCV) and a state of charge (SOC) of the battery pack in the balance state, to obtain an OCV and a SOC of each cell just before the battery pack is switched to the rest state; and obtaining an aging differential index according to the SOC of each cell just before the battery pack is switched to the rest state, the branch current of each cell just after the battery pack is switched to the rest state, and a rated capacity of the battery pack, to determine a relative aging level of the two cells.

Abstract: A method of determining an aging level of a battery includes utilizing a first charging device to charge a first battery; utilizing a second obtaining device to obtain a plurality of first steady open-circuit voltages (OCVs) of the first battery when a charging state of the first battery respectively reaches a plurality of first stop-charge conditions; utilizing a second charging device to charge a second battery; utilizing a third obtaining device to obtain a stop-charge parameter of the second battery and a second steady OCV of the second battery corresponding to the stop-charge parameter of the second battery; and utilizing an aging level determining device to determine an aging level of the second battery relative to the first battery according to the second steady OCV of the second battery and one of the first steady OCVs of the first battery corresponding to the stop-charge parameter of the second battery.

Abstract: A terminal device security management device and method are involved a terminal device management field. By grading network level, a level of functions being forbidden to be invoked, formed by obtaining a network connected by the terminal device, is sent to the terminal device for managing invoking operations of the functions. The terminal devices in different management domains are managed based on different connected networks for licensing the terminal device to invoke different function sets in different management domains. Work efficiency is improved, and a risk of leaks is reduced. A terminal device and a method of the terminal device are also disclosed. By responding information of a management device, a licensed function set is displayed in a display, or an invoking of the function is forbidden based on an invoking request for avoiding the specified function to be invoked in the management domain. The leak risk is further reduced.

Abstract: A first logic circuit included in a processor receives a first digital signal, where the first logic circuit includes a special purpose register, a comparator, and an adder, where the special purpose register stores a first resource balance for executing a smart contract, where the first digital signal includes a resource deduction quota corresponding to a code set in the smart contract. The first logic circuit reads the first resource balance from the special purpose register. The first logic circuit compares, using the comparator, the first resource balance with the resource deduction quota. In response to the first resource balance being greater than or equal to the resource deduction quota, the first logic circuit subtracts, using the adder, the resource deduction quota from the first resource balance to obtain a second resource balance. The first logic circuit stores the second resource balance in the special purpose register.

Abstract: A method of determining an aging level of a battery includes utilizing a first charging device to charge a first battery; utilizing a second obtaining device to obtain a plurality of first steady open-circuit voltages (OCVs) of the first battery when a charging state of the first battery respectively reaches a plurality of first stop-charge conditions; utilizing a second charging device to charge a second battery; utilizing a third obtaining device to obtain a stop-charge parameter of the second battery and a second steady OCV of the second battery corresponding to the stop-charge parameter of the second battery; and utilizing an aging level determining device to determine an aging level of the second battery relative to the first battery according to the second steady OCV of the second battery and one of the first steady OCVs of the first battery corresponding to the stop-charge parameter of the second battery.

Abstract: A method includes recording a branch current and a terminal voltage of each of two parallel connected cells of a battery pack during the battery pack being switched from a charging or discharging state through a rest state to a balance state, to obtain an internal resistance of each cell, and an open-circuit voltage (OCV) and a state of charge (SOC) of the battery pack in the balance state, to obtain an OCV and a SOC of each cell just before the battery pack is switched to the rest state; and obtaining an aging differential index according to the SOC of each cell just before the battery pack is switched to the rest state, the branch current of each cell just after the battery pack is switched to the rest state, and a rated capacity of the battery pack, to determine a relative aging level of the two cells.

Abstract: The present invention discloses an instruction processing apparatus, including: a first register adapted to store address information; a second register adapted to store address space identification information; a decoder adapted to receive and decode a translation lookaside buffer flush instruction, where the translation lookaside buffer flush instruction indicates that the first register serves as a first operand, and the second register serves as a second operand; and an execution unit coupled to the first register, the second register, and the decoder and executing the decoded translation lookaside buffer flush instruction, so as to acquire address information from the first register, to acquire address space identification information from the second register, and to broadcast the acquired address, information and address space identification information on a bus coupled to the instruction processing apparatus, so that another processing unit coupled to the bus performs purging on a translation lookaside

Abstract: A block device driver performs system boot using cache data and thus provides a mechanism that reduces disk/IO waiting time during system boot.