Abstract: A video signal receiving apparatus receives a first and second video signals for transmitting a same video content. When determining a size adjustment amount of a second video included in the second video signal, the video signal receiving apparatus performs scaling processing on a second image included in the second video signal to generate a scaling image and performs shift processing on the second image to generate a shift image. The video signal receiving apparatus calculates a similarity degree between a first image included in the first video signal and the scaling image, calculates a similarity degree between the first image and the shift image, and uses the scaling image or the shift image having the higher calculated similarity degree as an image to be subjected to the next scaling processing and the next shift processing.

Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section and a hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.

Abstract: A video signal receiving apparatus receives a first and second video signals for transmitting a same video content. When determining a size adjustment amount of a second video included in the second video signal, the video signal receiving apparatus performs scaling processing on a second image included in the second video signal to generate a scaling image and performs shift processing on the second image to generate a shift image. The video signal receiving apparatus calculates a similarity degree between a first image included in the first video signal and the scaling image, calculates a similarity degree between the first image and the shift image, and uses the scaling image or the shift image having the higher calculated similarity degree as an image to be subjected to the next scaling processing and the next shift processing.

Abstract: A display area can be smoothly moved. A semiconductor device sequentially receives a plurality of whole images, each of which includes a plurality of small screen images and which are temporally continuous and form a moving image, and decodes a received whole image. Here, the semiconductor device includes a reception unit that receives the whole image including the small screen images, a determination unit that determines a decoding area which includes a small screen image to be decoded and which is included in the whole image, and a decoding unit that decodes the small screen image in the decoding area which is determined by the determination unit and which is included in the whole image. The determination unit determines a new decoding area when a small screen image of intra frame appears in the decoding area.

Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section and a hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.

Abstract: A data processing system includes a plurality of data processing devices that perform in parallel data processing on the basis of initial setup data. The data processing devices each has a unique ID and includes a plurality of registers that store the initial setup data and a transfer circuit. The transfer circuit receives packets including a payload that is the initial setup data, shared information, a destination ID and a destination address and, when the shared information indicates that the payload is the initial setup data to be set commonly into the plurality of the data processing devices including its own data processing device, transfers the payload to the register that the destination address indicates irrespective of mismatching between the destination ID and its own ID.

Abstract: There is a problem that memory protection against access to a shared memory by a sub-arithmetic unit used by a program executed in a main-arithmetic unit cannot be performed in a related-art semiconductor device. According to one embodiment, a semiconductor device includes a sub-arithmetic unit configured to execute a process of a part of a program executed by a main-arithmetic unit, and a shared memory shared by the main-arithmetic unit and the sub-arithmetic unit, in which the sub-arithmetic unit includes a memory protection unit configured to permit or prohibit access to the shared memory based on an access permission range address value provided from the main-arithmetic unit, the access to the shared memory being access that arises from a process executed by the sub-arithmetic unit.

Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section and a hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.

Abstract: In a picture encoding device and a picture decoding device, the access to a reference frame memory is suppressed. The picture encoding device is comprised of a first encoder for intra picture encoding, a second encoder for inter picture encoding, and an intermediate buffer. A local decoded picture generated by the first encoder is stored as a reference picture in the intermediate buffer, and the inter picture encoding by the second encoder is performed by referring to the local decoded picture in the intermediate buffer. A picture decoding device is comprised of a first decoder for intra picture decoding, a second decoder for inter picture decoding, and an intermediate buffer. A local decoded picture generated by the first decoder is stored as a reference picture in the intermediate buffer, and the inter picture decoding by the second decoder is performed by referring the local decoded picture in the intermediate buffer.

Abstract: A semiconductor device includes a hash generator, a reference hash list, a frame mode determination unit, and an intra prediction unit. The hash generator generates a hash value of a target frame to be encoded. The reference hash list is to record the hash value generated by the hash generator. The frame mode determination unit compares the hash value generated by the hash generator and the hash value in the reference hash list. The intra prediction unit performs intra prediction for the target frame to be encoded. When the hash value of the target frame to be encoded coincides with any of the hash values in the reference hash list, the intra prediction unit skips an encoding process, and outputs encoded information corresponding to any of the hash values in the reference hash list.

Abstract: A semiconductor device includes a hash generator, a reference hash list, a frame mode determination unit, and an intra prediction unit. The hash generator generates a hash value of a target frame to be encoded. The reference hash list is to record the hash value generated by the hash generator. The frame mode determination unit compares the hash value generated by the hash generator and the hash value in the reference hash list. The intra prediction unit performs intra prediction for the target frame to be encoded. When the hash value of the target frame to be encoded coincides with any of the hash values in the reference hash list, the intra prediction unit skips an encoding process, and outputs encoded information corresponding to any of the hash values in the reference hash list.

Abstract: An object of the present invention is to detect a failure of a camera input in a system including a camera or a video transmission path (camera input). An image processor includes a hash derivation circuit having a computing unit that calculates hash values on an input screen and a storage circuit that stores the hash values. The image processor compares the hash values between multiple frames so as to decide whether the screens have changed or stopped. A failure is detected when the screens are stopped.

Abstract: To efficiently provide 2-dimensional display of 3-dimensional video stream. A video decoding device 100 includes a macro block selector 103 for sequentially selecting, as objects to be decoded, macro blocks belonging to a range required for 2-dimensional display, and a decoding unit 100 for sequentially decoding macro blocks selected by the macro block selector. Furthermore, the video decoding device includes a motion vector shift unit 108 for correcting, when a motion vector of a macro block selected by the macro block selector is referring to outside the range required for the 2-dimensional display, the reference indicated by the motion vector to be within the range required for the 2-dimensional display. Since the macro block selector performs block selection, the decoding unit skips processing of macro blocks which are not supposed to be 2-dimensionally displayed.

Abstract: A display area can be smoothly moved. A semiconductor device sequentially receives a plurality of whole images, each of which includes a plurality of small screen images and which are temporally continuous and form a moving image, and decodes a received whole image. Here, the semiconductor device includes a reception unit that receives the whole image including the small screen images, a determination unit that determines a decoding area which includes a small screen image to be decoded and which is included in the whole image, and a decoding unit that decodes the small screen image in the decoding area which is determined by the determination unit and which is included in the whole image. The determination unit determines a new decoding area when a small screen image of intra frame appears in the decoding area.

Abstract: To efficiently provide 2-dimensional display of a 3-dimensional video Stream. A video decoding device 100 includes a macro block selector 103 for sequentially selecting, as objects to be decoded, macro blocks belonging to a range required for 2-dimensional display, and a decoding unit 100 for sequentially decoding macro blocks selected by the macro block selector. Furthermore, the video decoding device includes a motion vector shift unit 108 for correcting, when a motion vector of a macro block selected by the macro block selector is referring to outside the range required for the 2-dimensional display, the reference indicated by the motion vector to be within the range required for the 2-dimensional display. Since the macro block selector performs block selection, the decoding unit skips processing of macro blocks which are not supposed to be 2-dimensionally displayed.

Abstract: There is a problem that memory protection against access to a shared memory by a sub-arithmetic unit used by a program executed in a main-arithmetic unit cannot be performed in a related-art semiconductor device. According to one embodiment, a semiconductor device includes a sub-arithmetic unit configured to execute a process of a part of a program executed by a main-arithmetic unit, and a shared memory shared by the main-arithmetic unit and the sub-arithmetic unit, in which the sub-arithmetic unit includes a memory protection unit configured to permit or prohibit access to the shared memory based on an access permission range address value provided from the main-arithmetic unit, the access to the shared memory being access that arises from a process executed by the sub-arithmetic unit.

Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section. and a. hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.

Abstract: An image receiving method for a decoder, includes receiving an encoding stream multiplexed into three levels of sequence, picture, and slice, receiving an environmental information of an image receiving device and determining a parameter to be changed in the image encoding stream based on the environmental information of the image receiving device, changing a parameter at the sequence level, changing a parameter at the picture level and at the sequence level for each picture based on information indicating accuracy of image recognition, and statistical information obtained by decoding, and changing a parameter in the slice header based on the information indicating accuracy of image recognition, and the statistical information obtained by decoding.

Abstract: A semiconductor device includes a hash generator, a reference hash list, a frame mode determination unit, and an intra prediction unit. The hash generator generates a hash value of a target frame to be encoded. The reference hash list is to record the hash value generated by the hash generator. The frame mode determination unit compares the hash value generated by the hash generator and the hash value in the reference hash list. The intra prediction unit performs intra prediction for the target frame to be encoded. When the hash value of the target frame to be encoded coincides with any of the hash values in the reference hash list, the intra prediction unit skips an encoding process, and outputs encoded information corresponding to any of the hash values in the reference hash list.

Abstract: To improve an image recognition rate by quickly changing a parameter in a proper manner without being affected by a transmission delay of an image encoding stream in an image receiving device that recognizes a decoded image obtained by decoding the received image encoding stream. The image receiving device includes a data receiving unit, a parameter changing unit, a decoding unit, and an image recognition unit. The data receiving unit receives an image encoding stream including image encoding data and the parameter. The parameter changing unit changes the parameter received by the data receiving unit, that is, the parameter specified for encoding performed by a sender, to a value suitable for image recognition performed in the subsequent stage. The decoding unit generates the image decoding data by decoding the received image encoding data according to the changed parameter. The image recognition unit performs image recognition on the image decoding data.