Patents by Inventor Ren-Peng Huang
Ren-Peng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9748144Abstract: First and second semiconductor structures, a CESL, and an ILD layer are formed on a substrate. The first semiconductor structure includes first dummy gate, first nitride mask, and first oxide mask. The second semiconductor structure includes second dummy gate, second nitride mask, and second oxide mask. A first planarization is performed to remove a portion of the ILD layer, exposing CESL. A portion of the CESL, a portion of the ILD layer, the first and the second oxide masks are removed. A hard mask layer is formed on the first and the second nitride masks, and in a recess of the ILD layer. A second planarization is performed to remove a portion of the hard mask layer, the first and the second nitride masks, exposing first and second dummy gates. A remaining portion of the hard mask layer covers the ILD layer.Type: GrantFiled: April 26, 2016Date of Patent: August 29, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Ling Lin, Yi-Wen Chen, Chen-Ming Huang, Ren-Peng Huang, Ching-Fu Lin
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Patent number: 8940600Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the resistor region of the substrate; forming a tank in the STI; and forming a resistor in the tank and on two sides of the top surface of the STI outside the tank.Type: GrantFiled: June 3, 2014Date of Patent: January 27, 2015Assignee: United Microelectronics Corp.Inventors: Chun-Wei Hsu, Po-Cheng Huang, Ren-Peng Huang, Jie-Ning Yang, Chia-Lin Hsu, Teng-Chun Tsai, Chih-Hsun Lin, Chang-Hung Kung, Yen-Ming Chen, Yu-Ting Li
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Publication number: 20140273371Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the resistor region of the substrate; forming a tank in the STI; and forming a resistor in the tank and on two sides of the top surface of the STI outside the tank.Type: ApplicationFiled: June 3, 2014Publication date: September 18, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Wei Hsu, Po-Cheng Huang, Ren-Peng Huang, Jie-Ning Yang, Chia-Lin Hsu, Teng-Chun Tsai, Chih-Hsun Lin, Chang-Hung Kung, Yen-Ming Chen, Yu-Ting Li
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Patent number: 8828745Abstract: A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.Type: GrantFiled: July 6, 2011Date of Patent: September 9, 2014Assignee: United Microelectronics Corp.Inventors: Wei-Che Tsao, Chia-Lin Hsu, Jen-Chieh Lin, Teng-Chun Tsai, Hsin-Kuo Hsu, Ya-Hsueh Hsieh, Ren-Peng Huang, Chih-Hsien Chen, Wen-Chin Lin, Yung-Lun Hsieh
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Patent number: 8779526Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the substrate of the resistor region; forming a tank in the STI of the resistor region; and forming a resistor in the tank and on the surface of the STI adjacent to two sides of the tank.Type: GrantFiled: October 28, 2011Date of Patent: July 15, 2014Assignee: United Microelectronics Corp.Inventors: Chun-Wei Hsu, Po-Cheng Huang, Ren-Peng Huang, Jie-Ning Yang, Chia-Lin Hsu, Teng-Chun Tsai, Chih-Hsun Lin, Chang-Hung Kung, Yen-Ming Chen, Yu-Ting Li
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Patent number: 8759219Abstract: A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.Type: GrantFiled: January 24, 2011Date of Patent: June 24, 2014Assignee: United Microelectronics Corp.Inventors: Ya-Hsueh Hsieh, Teng-Chun Tsai, Wen-Chin Lin, Hsin-Kuo Hsu, Ren-Peng Huang, Chih-Hsien Chen, Chih-Chin Yang, Hung-Yuan Lu, Jen-Chieh Lin, Wei-Che Tsao
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Publication number: 20130105912Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the substrate of the resistor region; forming a tank in the STI of the resistor region; and forming a resistor in the tank and on the surface of the STI adjacent to two sides of the tank.Type: ApplicationFiled: October 28, 2011Publication date: May 2, 2013Inventors: Chun-Wei Hsu, Po-Cheng Huang, Ren-Peng Huang, Jie-Ning Yang, Chia-Lin Hsu, Teng-Chun Tsai, Chih-Hsun Lin, Chang-Hung Kung, Yen-Ming Chen, Yu-Ting Li
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Publication number: 20130011938Abstract: A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.Type: ApplicationFiled: July 6, 2011Publication date: January 10, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei-Che TSAO, Chia-Lin Hsu, Jen-Chieh Lin, Teng-Chun Tsai, Hsin-Kuo Hsu, Ya-Hsueh Hsieh, Ren-Peng Huang, Chih-Hsien Chen, Wen-Chin Lin, Yung-Lun Hsieh
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Publication number: 20120187563Abstract: A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.Type: ApplicationFiled: January 24, 2011Publication date: July 26, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ya-Hsueh HSIEH, Teng-Chun Tsai, Wen-Chin Lin, Hsin-Kuo Hsu, Ren-Peng Huang, Chih-Hsien Chen, Chih-Chin Yang, Hung-Yuan Lu, Jen-Chieh Lin, Wei-Che Tsao